MCP2510-I/SO Microchip Technology, MCP2510-I/SO Datasheet - Page 39

• Manufacturer Part Number: MCP2510-I/SO
• Description: IC CAN CONTRLER IND TEMP 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2510-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.10
The configuration registers (CNF1, CNF2, CNF3) con-
trol the bit timing for the CAN bus interface. These reg-
isters can only be modified when the MCP2510 is in
configuration mode (see Section 9.0).
5.10.1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of T
input frequency, with the minimum length of T
OSC1 clock cycles in length (when BRP<5:0> are set
to 000000). The SJW<1:0> bits select the synchroni-
zation jump width in terms of number of T
5.10.2
The PRSEG<2:0> bits set the length, in T
propagation segment. The PHSEG1<2:0> bits set the
length, in T
trols how many times the RXCAN pin is sampled. Set-
REGISTER 5-1:
© 2007 Microchip Technology Inc.
Bit Timing Configuration
Registers
bit 7-6
bit 5-0
Q
CNF1
CNF2
’s, of phase segment 1. The SAM bit con-
CNF1 - CONFIGURATION REGISTER1 (ADDRESS: 2Ah)
bit 7
SJW<1:0>: Synchronization Jump Width Length
11 = Length = 4 x T
10 = Length = 3 x T
01 = Length = 2 x T
00 = Length = 1 x T
BRP<5:0>: Baud Rate Prescaler
T
Legend:
R = Readable bit
-n = Value at POR
Q
R/W-0
SJW1
= 2 x (BRP + 1) / F
Q
relative to the OSC1
R/W-0
SJW0
Q
’s.
Q
Q
Q
Q
Q
Q
’s, of the
OSC
being 2
R/W-0
BRP5
W = Writable bit
’1’ = Bit is set
R/W-0
BRP4
ting this bit to a ‘1’ causes the bus to be sampled three
times; twice at T
at the normal sample point (which is at the end of phase
segment 1). The value of the bus is determined to be
the value read during at least two of the samples. If the
SAM bit is set to a ‘0’ then the RXCAN pin is sampled
only once at the sample point. The BTLMODE bit con-
trols how the length of phase segment 2 is determined.
If this bit is set to a ‘1’ then the length of phase segment
2 is determined by the PHSEG2<2:0> bits of CNF3
(see Section 5.10.3). If the BTLMODE bit is set to a ‘0’
then the length of phase segment 2 is the greater of
phase segment 1 and the information processing time
(which is fixed at 2 T
5.10.3
The PHSEG2<2:0> bits set the length, in T
Phase Segment 2, if the CNF2.BTLMODE bit is set to
a ‘1’. If the BTLMODE bit is set to a ‘0’ then the
PHSEG2<2:0> bits have no effect.
R/W-0
BRP3
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CNF3
Q
/2 before the sample point, and once
Q
R/W-0
BRP2
for the MCP2510).
MCP2510
x = Bit is unknown
R/W-0
BRP1
DS21291F-page 39
R/W-0
BRP0
Q
’s, of
bit 0