MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 26

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet (eTSEC), MII Management
26
Output differential voltage
Output offset voltage
Output impedance (single
ended)
Mismatch in a pair
Change in V
Change in V
Output current on short to GND
Notes:
1. This will not align to DC-coupled SGMII.
2. |V
3. The |V
4. V
5. The |V
variation (V
2 and 3) bit field of MPC8544E SerDes 2 control register 1:
•The MSbit (bit 0) of the above bit field is set to zero (selecting the full V
•The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in this table.
OS
OD
is also referred to as output common mode voltage.
| = |V
OD
OD
Parameter
| value shown in the table assumes the following transmit equalization setting in the XMITEQCD (for SerDes 2 lane
| value shown in the Typ column is based on the condition of XV
OD
OS
SD2_TXn
OS
between 0 and 1
between 0 and 1
= 500 mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n].
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
– V
SD2_TXn
2,3,5
Table 24. DC Transmitter Electrical Characteristics (continued)
|. |V
Symbol
I
Δ|V
SA
|V
ΔV
OD
ΔR
V
R
OD
, I
OS
O
OD
OS
| is also referred as output differential peak voltage. V
O
SB
|
|
Min
323
296
269
243
215
189
162
425
40
—
—
—
—
Typ
500
459
417
376
333
292
250
500
—
—
—
—
—
DD-DIFF-p-p
DD_SRDS2-Typ
amplitude—power up default);
577.5
Max
725
665
604
545
483
424
362
60
10
25
25
40
= 1.0 V, no common mode offset
TX-DIFFp-p
Freescale Semiconductor
= 2*|V
Unit
mV
mV
mV
mV
mA
%
Ω
OD
|
.
setting: 1.09x
setting: 1.33x
setting: 1.71x
Equalization
setting: 1.0x
Equalization
Equalization
setting: 1.2x
Equalization
Equalization
setting: 1.5x
Equalization
Equalization
setting: 2.0x
Notes
1, 4
—
—
—
—
—