MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 113

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.10 Guidelines for High-Speed Interface Termination
This section provides guidelines for when the SerDes interface is either not used at all or only partly used.
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section. However, the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
The following pins must be connected to GND:
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
The following pins must be connected to GND if not used:
21.11 Guideline for PCI Interface Termination
PCI termination, if not used at all, is done as follows.
Option 1
Freescale Semiconductor
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SD_TX[0:7]
SD_TX[0:7]
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
SD_TX[0:7]
SD_TX[0:7]
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
If PCI arbiter is enabled during POR,
All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OV
It is optional to disable PCI block through DEVDISR register after POR reset.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
through a single 10-kΩ resistor.
System Design Information
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