MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 97

• Manufacturer Part Number: MPC8347VRADDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Number
Rev.
3
2
1
0
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
11/2006
8/2006
4/2006
3/2006
Date
Initial public release.
• Updated note in introduction.
• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA
• In Table 5, “MPC8347EA Typical I/O Power Dissipation,” added GV
•
• In Section 23, “Ordering Information,” replicated note from document introduction.
• Changed all references to revision 2.0 silicon to revision 3.0 silicon.
• Changed VIH minimum value in Table 39, “JTAG Interface DC Electrical Characteristics,” to
• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
• In Table 63, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
• Removed Table 20, “Timing Parameters for DDR2-400.”
• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
• Changed Min and Max values for V
• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
parts for all silicon revisions, and 400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3.
added table footnote to designate rates that apply only to the TBGA package.
OV
= 2 and max = OV
= 2 and max = OV
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’
DD
Table 72. Document Revision History (continued)
– 0.3.
DD
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Substantive Change(s)
IH
and VIL in Table 40,“PCI DC Electrical Characteristics.”
DD
1.8-V values for DDR2;
Document Revision History
97