MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 91

IC MPU POWERQUICC II 620-PBGA

MPC8347VRADDB

Manufacturer Part Number
MPC8347VRADDB
Description
IC MPU POWERQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets

Specifications of MPC8347VRADDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
266MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
266 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
266MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA
system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system
designer should place at least one decoupling capacitor at each V
device. These capacitors should receive their power from separate V
power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under
the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the V
and LV
have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
21.4
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OV
connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the MPC8347EA.
21.5
The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the
driver is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
Freescale Semiconductor
DD
Connection Recommendations
Output Buffer DC Impedance
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
DD
, GV
DD
, or LV
DD
as required. Unused active high inputs should be
P
is trimmed until the voltage at the pad equals
DD
2
C).
, GV
DD
, OV
DD
DD
, OV
, LV
DD
, GV
DD
DD
DD
, GV
, OV
/2 (see
DD
, and LV
System Design Information
DD
DD
DD
, LV
, and GND pins of
Figure
, OV
DD
DD
DD
, and GND
43). The
pin of the
, GV
DD
DD
,
91

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