MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 77

• Manufacturer Part Number: MPC8347VRADDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
Addressed by This Document,”
or authorized distributor for more information.
1
2
3
4
Table 59
conditions.
Freescale Semiconductor
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLKn)
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
USB_DR, USB_MPH maximum internal operating
frequency
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLKn)
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
USB_DR, USB_MPH maximum internal operating
frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2× the DDR memory bus frequency.
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2x the DDR memory bus frequency.
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
provides the operating frequencies for the MPC8347EA PBGA under recommended operating
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Characteristic
Parameter
4
4
1
1
2
3
2
3
Table 59. Operating Frequencies for PBGA
Table 58. Operating Frequencies for TBGA
for part ordering details and contact your Freescale Sales Representative
266–400
100–266
100–133
100–133
16.67–133
25–66
133
133
400 MHz
266 MHz
200–266
266–533
100–333
100–133
100–200
16.67–133
25–66
133
133
16.67–133
533 MHz
333 MHz
200–333
100–266
100–133
100–133
25–66
133
133
266–667
100–333
100–166.67
100–200
16.67–133
25–66
166
166
667 MHz
400 MHz
200–400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clocking
Unit
Unit
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