MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 15

• Manufacturer Part Number: MPC8347VRADDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11
6
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8347EA. Note that DDR SDRAM is GV
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
6.1
Table 12
MPC8347EA when GV
Freescale Semiconductor
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
results in the minimum and an 8:1 ratio results in the maximum.
DDR and DDR2 SDRAM
lists the PLL and DLL lock times.
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
DDR and DDR2 SDRAM DC Electrical Characteristics
Parameter/Condition
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See
Document,” for silicon revision level determination.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
Parameter/Condition
OUT
= 1.420 V)
DD
(typ) = 1.8 V
Section 22.1, “Part Numbers Fully Addressed by This
Table 11. PLL and DLL Lock Times
.
Symbol
MV
GV
V
I
V
I
V
OZ
OH
TT
REF
IH
IL
DD
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
NOTE
MV
MV
0.49 × GV
REF
REF
–13.4
1.71
–0.3
–9.9
Min
7680
+ 0.125
Section 19, “Clocking.”
Min
– 0.04
—
DD
MV
122,880
MV
0.51 × GV
GV
Max
100
REF
REF
DD
Max
1.89
DD
9.9
—
– 0.125
+ 0.04
+ 0.3
(typ) = 1.8 V
DD
csb_clk cycles
DDR and DDR2 SDRAM
Unit
μs
DD
Unit
mA
μA
V
V
V
V
V
(typ) = 1.8 V.
Notes
Notes
1, 2
—
—
—
—
1
2
3
4
15