MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 96

• Manufacturer Part Number: MPC8347VRADDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document Revision History
96
Number
Rev.
8
7
6
5
4
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
12/2006
2/2009
4/2007
3/2007
1/2007
Date
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T
from 900 ps to 775 ps.
• Added footnote 6 to
• In
• In
• Added footnote 10 and 11 to
• In
• In
• In
• In
• Added footnote 4 to
• In
• In
• In
• In
• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to t
•
• In Figure 43, “JTAG Interface Connection,” updated with new figure.
• In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’
• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
• In Section 23, “Ordering Information,” replaced first paragraph and added a note.
• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
• In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency).
• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply
• In Table 4, “MPC8347EA Power Dissipation,” added two footnotes to 667-MHz row showing
• In Table 54, “MPC8347EA (TBGA) Pinout Listing,” updated V
in DLL bypass mode). Similarly, made the same correction to
for output signals.
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
is limited to 533 (TBGA) and 400 (PBGA) with a platform frequency of 266.”
added USB to the seventh row.
paragraph, added a new paragraph.
and deleted original note 3; renumbered the remaining notes.
row, changed the value in the 533 MHz column to 100-333.
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,
changed the CORE PLL value to 0000110.
voltage of 1.3 V for 667-MHz parts.
nominal core supply voltage of 1.3 V for 667-MHz parts.
voltage of 1.3 V for 667-MHz parts.
Table
Table
Section 9.2, “USB AC Electrical
Section 21.1, “System
Section 21.2, “PLL Power Supply
Table
Table
Table
Table
Section 21.7, “Pull-Up Resistor
Table 72. Document Revision History (continued)
39, corrected t
70, updated note 1 to say the following: “For temperature range = C, processor frequency
58, corrected the max csb_clk to 266 MHz.
64, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz
3,
4,
“Output Drive Capability,”
“Operating Frequencies for TBGA,”
Table
Table
LBKHOV
Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
7.
70.
Table 55
parameter to t
Requirements,“ deleted last two paragraphs and after first
Substantive Change(s)
Specifications,” clarified that AC table is for ULPI only.
Filtering,” in the second paragraph, changed “provide five
changed the values in the Output Impedance column and
and
Table
LBKLOV
added column for 400 MHz.
56.
(output data is driven on falling edge of clock
DD
Figure
row to show nominal core supply
21,
Figure
Freescale Semiconductor
ddkhds
23, and
for 333 MHz
Figure 24
CISKEW