XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 383
XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BITSLIP Submodule
R
Bitslip Operation
All ISERDES blocks in Virtex-4 devices contain a Bitslip submodule. Bitslip shifts the
parallel data in the ISERDES block, allowing every combination of a repeating serial
pattern received by the deserializer to be presented to the FPGA logic. This repeating serial
pattern is typically called a training pattern (training patterns are supported by many
networking and telecommunication standards).
By asserting the Bitslip pin of the ISERDES block, the incoming serial data stream is
reordered at the parallel side. This operation is repeated until the training pattern is seen.
The tables in
For illustrative purposes the data width is eight. The Bitslip operation is synchronous to
CLKDIV. In SDR mode, every Bitslip operation causes the output pattern to shift left by
one. In DDR mode, every Bitslip operation causes the output pattern to alternate between
a shift right by one and shift left by three. In this example, on the eighth Bitslip operation,
the output pattern reverts to the initial pattern. This assumes that serial data is an eight bit
repeating pattern.
Figure 8-11
TRUE. Two ISERDES modules are in a master-slave configuration for a data width of eight.
);
.CE2 (open),
.CLK (clk),
.CLKDIV (clkdiv),
.D (data_input),
.DLYCE (dlyce),
.DLYINC (dlyinc),
.DLYRST (dlyrst),
.OCLK (open),
.REV (open),
.SHIFTIN1 (open),
.SHIFTIN2 (open),
.SR (rst),
illustrates the ISERDES configured in 1:8 SDR mode with Bitslip_Enable set to
Bitslip Operation in SDR Mode
Figure 8-10
Operations
Executed
Bitslip
Initial
1
2
3
4
5
6
7
Figure 8-10: Bitslip Operation Examples
illustrate the effects of a Bitslip operation in SDR and DDR mode.
www.xilinx.com
Pattern (8:1)
10010011
00100111
01001110
10011100
00111001
01110010
11100100
11001001
Output
Input Serial-to-Parallel Logic Resources (ISERDES)
Bitslip Operation in DDR Mode
Operations
Executed
Bitslip
Initial
1
2
3
4
5
6
7
Pattern (8:1)
00100111
10010011
10011100
01001110
01110010
00111001
11001001
11100100
ug070_8_16_072604
Output
383
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