XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 398
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
XC4VFX12-10FFG668I
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Chapter 8: Advanced SelectIO Logic Resources
398
OSERDES VHDL and Verilog Instantiation Templates
OSERDES VHDL Template
The following examples illustrate the instantiation of the OSERDES module in VHDL and
Verilog.
--Example OSERDES Component Declaration
component OSERDES
--Example OSERDES instantiation
U_OSERDES : OSERDES
Port map (
generic(
port(
end component;
);
);
OQ: out std_ulogic;
SHIFTOUT1: out std_ulogic;
SHIFTOUT2: out std_ulogic;
TQ: out std_ulogic;
CLK: in std_ulogic;
CLKDIV: in std_ulogic;
D1: in std_ulogic;
D2: in std_ulogic;
D3: in std_ulogic;
D4: in std_ulogic;
D5: in std_ulogic;
D6: in std_ulogic;
OCE: in std_ulogic;
REV
SHIFTIN1: in std_ulogic;
SHIFTIN2: in std_ulogic;
SR
T1: in std_ulogic;
T2: in std_ulogic;
T3: in std_ulogic;
T4: in std_ulogic;
TCE: in std_ulogic
OQ => user_oq,
SHIFTOUT1 => user_shiftout1,
SHIFTOUT2 => user_shiftout2,
TQ => user_tq,
DATA_RATE_OQ: string:= "DDR";
DATA_RATE_TQ: string:= "DDR";
DATA_WIDTH: integer:= 4;
INIT_OQ: bit:= '0';
INIT_TQ: bit:= '0';
SERDES_MODE: string:= "MASTER";
SRVAL_OQ: bit:= '0';
SRVAL_TQ: bit:= '0';
TRISTATE_WIDTH: integer:= 4
: in std_ulogic;
: in std_ulogic;
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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