XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 335
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Note on Instability after an Increment/Decrement Operation
Figure 7-12
Clock Event 1
On the rising edge of C, a reset is detected, causing the output O to select tap 0 as the
output from the 64-tap chain (assuming IOBDELAY_VALUE = 0).
Clock Event 2
A pulse on CE and INC is captured on the rising edge of C. This indicates an Increment
operation. For the remainder of the cycle associated with clock event 2, the output is
changing from tap 0 to tap 1. During this time, the output may be unstable and contain
erroneous data.
Clock Event 3
By this time, the output has stabilized at tap 1, thus completing the Increment operation.
The output remains at tap 1 indefinitely until there is further activity on the RST, CE, or
INC pins.
In
another. If the IDELAY output is sampled during that period of instability, the captured
data may be incorrect. In the case where the IDELAY output is sampled by the same clock
that is connected to the C input, there is no danger of capturing a bit during the unstable
period because the settling time is less than one period of clock C.
However, IDELAY is often used in conjunction with an ISERDES or an IDDR element.
These elements sample the output of IDELAY at a much higher rate than the clock
connected to the C input of IDELAY. The result is that data is sampled during the unstable
period (resulting in at most one bit error). This potentially corrupt sample must propagate
through the ISERDES or IDDR before becoming visible to the user. When the potential bit
error emerges, the user should treat it as corrupted. The user must examine the latency of
the ISERDES or IDDR being used (it differs depending on modes) to determine when the
data is valid again. If a small increase in latency is not a concern, the user can wait 4
CLKDIV cycles when using an ISERDES or 4 CLK cycles when using an IDDR. This is a
Figure 7-12
RST
INC
CE
O
C
shows an IDELAY timing diagram. It is assumed that IOBDELAY_VALUE = 0.
there is a period of instability when the output is changing from one tap to
Event 1
Clock
Figure 7-12: IDELAY Timing Diagram
www.xilinx.com
Tap 0
Event 2
Clock
Event 3
Clock
Tap 1
ILOGIC Resources
UG070_c7_12_032507
335
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