XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 151
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668I
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10 000
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FIFO Operations
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Reset
Operating Mode
Status Flags
R
Standard Mode
First Word Fall Through (FWFT) Mode
Empty Flag
Reset is an asynchronous signal to reset all read and write address counters, and must be
asserted to initialize flags after power up. Reset does not clear the memory, nor does it clear
the output register. When reset is asserted High, EMPTY and ALMOST_EMPTY will be set
to 1, FULL and ALMOST_FULL will be reset to 0. The reset signal must be High for at least
three read clock and write clock cycles to ensure all internal states are reset to the correct
values. During RESET, RDEN and WREN must be held Low.
There are two operating modes in FIFO functions. They differ only in output behavior after
the first word is written to a previously empty FIFO.
After the first word is written into an empty FIFO, the Empty flag deasserts synchronously
with RDCLK. After Empty is deasserted Low and RDEN is asserted, the first word will
appear at DO on the rising edge of RDCLK.
After the first word is written into an empty FIFO, it automatically appears at DO without
asserting RDEN. Subsequent Read operations require Empty to be Low and RDEN to be
High.
The Empty flag is synchronous with RDCLK, and is asserted when the last entry in the
FIFO is read. When there are no more valid entries in the FIFO queue, the read pointer will
be frozen. The Empty flag is deasserted at three (in standard mode) or four (in FWFT
mode) read clocks after new data is written into the FIFO.
DO (Standard)
DO (FWFT)
Figure 4-16
EMPTY
RDCLK
RDEN
Figure 4-16: Read Cycle Timing (Standard and FWFT Modes)
illustrates the difference between standard mode and FWFT mode.
www.xilinx.com
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