XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 53
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BUFR VHDL and Verilog Templates
R
VHDL Template
Verilog Template
The following examples illustrate the instantiation of the BUFR module in VHDL and
Verilog.
--Example BUFR declaration
component BUFR
generic(
);
--Example BUFR instantiation
U_BUFR : BUFR
Port map (
--Declaring constraints in VHDL file
attribute BUFR_DIVIDE
attribute LOC : string;
attribute INIT_OUT of U_BUFR: label is BYPASS;
attribute LOC of U_BUFR: label is "BUFR_X#Y#";
--where # is valid integer locations of BUFR
//Example BUFR module declaration
module BUFR (O, CE, CLR, I);
endmodule;
//Example BUFR instantiation
BUFR U_BUFR (
.O(user_o),
.CE(user_ce),
.CLR(user_clr),
port(
end component;
);
O => user_o,
CE => user_ce,
CLR => user_clr,
I => user_i
);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
BUFR_DIVIDE
O: out std_ulogic;
CE: in
CLR: in
I: in
std_ulogic
std_ulogic;
std_ulogic;
www.xilinx.com
: string := "BYPASS";
: string;
VHDL and Verilog Templates
53
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