XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 264
XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Price
Company:
Part Number:
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Chapter 6: SelectIO Resources
264
HSTL_ II, HSTL_ IV, HSTL_ II_18, HSTL_ IV_18 Usage
HSTL_ II_DCI, HSTL_ IV_DCI, HSTL_ II_DCI_18, HSTL_ IV_DCI_18 Usage
DIFF_HSTL_ II, DIFF_HSTL_II_18
DIFF_HSTL_II_DCI, DIFF_HSTL_II_DCI_18
HSTL_II uses V
parallel termination voltage (V
bidirectional links.
HSTL_II_DCI provides on-chip split thevenin termination powered from V
an equivalent termination voltage of V
to V
links.
Differential HSTL class II pairs complimentary single-ended HSTL_II type drivers with a
differential receiver. Differential HSTL Class II is intended to be used in bidirectional links.
Differential HSTL can also be used for differential clock and DQS signals in memory
interface designs.
Differential HSTL class II pairs complimentary single-ended HSTL_II type drivers with a
differential receiver, including on-chip differential termination. Differential HSTL Class II
is intended to be used in bidirectional links. Differential HSTL can also be used for
differential clock and DQS signals in memory interface designs.
CCO
(V
TT
). HSTL_II_DCI and HSTL_IV_ DCI are intended to be used in bidirectional
CCO
/2 as a parallel termination voltage (V
www.xilinx.com
TT
). HSTL_II and HSTL_IV are intended to be used in
CCO
/2. HSTL_IV_ DCI provides single termination
TT
). HSTL_IV uses V
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
CCO
CCO
, creating
as a
R
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