XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 218
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
218
Attributes
Content Initialization - INIT
Initialization in VHDL or Verilog Codes
Location Constraints
With the INIT attributes, users can define the initial memory contents after configuration.
By default distributed RAM is initialized with all zeros during the device configuration
sequence. The initialization attribute INIT represents the specified memory contents. Each
INIT is a hex-encoded bit vector.
primitive.
Table 5-11: INIT Attributes Length
Distributed RAM structures can be initialized in VHDL or Verilog code for both synthesis
and simulation. For synthesis, the attributes are attached to the distributed RAM
instantiation and are copied in the EDIF output file to be compiled by Xilinx Alliance Series
tools. The VHDL code simulation uses a generic parameter to pass the attributes. The
Verilog code simulation uses a defparam parameter to pass the attributes.
The distributed RAM instantiation templates (in VHDL and Verilog) illustrate these
techniques
The CLB has four slices S0, S1, S2 and S3. As an example, in the bottom left CLB, the slices
have the coordinates shown in
Distributed RAM instances can have LOC properties attached to them to constrain
placement. The RAM16X1S primitive fits in any LUT of slices S0 or S2.
For example, the instance U_RAM16 is placed in slice X0Y0 with the following LOC
properties:
Distributed RAM placement locations use the slice location naming convention, allowing
LOC properties to transfer easily from array to array.
INST "U_RAM16" LOC = "SLICE_X0Y0";
RAM16X1D
RAM16X1S
RAM32X1S
RAM64X1S
Primitive
(“VHDL and Verilog
www.xilinx.com
Figure
Templates”).
Table 5-11
5-1.
Template
RAM_16S
RAM_32S
RAM_64S
RAM_16S
shows the length of the INIT attribute for each
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
INIT Attribute Length
16 digits
4 digits
8 digits
4 digits
R
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