XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 35
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
BUFGMUX_VIRTEX4
BUFGMUX_VIRTEX4 is a clock buffer with two clock inputs, one clock output, and a select
line. This primitive is based on BUFGCTRL with some pins connected to logic High or
Low.
BUFGMUX_VIRTEX4 uses the S pins as select pins. S can switch anytime without causing
a glitch. The setup/hold times on S determine whether the output will pass an extra pulse
of the previously selected clock before switching to the new clock. If S changes as shown in
Figure
then the output will not pass an extra pulse of I0. If S changes following the hold time for
S, then the output will pass an extra pulse. If S violates the setup/hold requirements, the
output might pass the extra pulse, but it will not glitch. In any case, the output changes to
the new clock within three clock cycles of the slower clock.
The setup/hold requirements for S0 and S1 are with respect to the falling clock edge
(assuming INIT_OUT = 0), not the rising edge as for CE0 and CE1.
Switching conditions for BUFGMUX_VIRTEX4 are the same as the S pin of BUFGCTRL.
Figure 1-12
Other capabilities of the BUFGMUX_VIRTEX4 primitive are:
•
•
Pre-selection of I0 and I1 input after configuration.
Initial output can be selected as High or Low after configuration.
Figure 1-11
1-12, prior to the setup time T
I1
I0
S
illustrates the timing diagram for BUFGMUX_VIRTEX4.
BUFGMUX_VIRTEX4
I 0
I1
O
S
illustrates the relationship of BUFGMUX_VIRTEX4 and BUFGCTRL.
Figure 1-12: BUFGMUX_VIRTEX4 Timing Diagram
Figure 1-11: BUFGMUX_VIRTEX4 as BUFGCTRL
www.xilinx.com
T
BCCKO_O
O
BCCCK_S
S
and before I0 transitions from High to Low,
GND
GND
V
V
DD
DD
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
Global Clocking Resources
BCCKO_O
ug070_1_11_071304
ug070_1_12_080204
O
35
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