XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 381
![no-image](/images/no-image-200.jpg)
XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668I
Manufacturer:
Xilinx Inc
Quantity:
10 000
- Current page: 381 of 406
- Download datasheet (6Mb)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
NETWORKING)
VARIABLE)
port (
end component;
-- Component Attribute specification for ISERDES
-- should be placed after architecture declaration but
-- before the "begin" keyword
attribute BITSLIP_ENABLE : string;
attribute DATA_RATE : string;
attribute DATA_WIDTH : integer;
attribute INTERFACE_TYPE : string;
attribute IOBDELAY : string;
attribute IOBDELAY_TYPE : string;
attribute IOBDELAY_VALUE : integer;
attribute NUM_CE : integer;
attribute SERDES_MODE : string;
-- Component Instantiation for ISERDES should be placed
-- in architecture after the "begin" keyword
--
-- Instantiation Section
--
U1 : ISERDES
generic map (
);
O : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC;
Q5 : out STD_LOGIC;
Q6 : out STD_LOGIC;
SHIFTOUT1 : out STD_LOGIC;
SHIFTOUT2 : out STD_LOGIC;
BITSLIP : in STD_LOGIC;
CE1 : in STD_LOGIC;
CE2 : in STD_LOGIC;
CLK : in STD_LOGIC;
CLKDIV : in STD_LOGIC;
D : in STD_LOGIC;
DLYCE : in STD_LOGIC;
DLYINC : in STD_LOGIC;
DLYRST : in STD_LOGIC;
OCLK : in STD_LOGIC;
REV : in STD_LOGIC;
SHIFTIN1 : in STD_LOGIC;
SHIFTIN2 : in STD_LOGIC;
SR : in STD_LOGIC;
);
INTERFACE_TYPE : string := "MEMORY"; --(MEMORY,
IOBDELAY : string := "NONE"; --(NONE,IBUF,IFD,BOTH)
IOBDELAY_TYPE : string := "DEFAULT"; --(DEFAULT,FIXED,
IOBDELAY_VALUE : integer := 0; --(0 to 63)
NUM_CE : integer := 2; --(1,2)
SERDES_MODE : string := "MASTER"; --(MASTER, SLAVE)
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
381
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