XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 229
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XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
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Company:
Part Number:
XC4VFX12-10FFG668I
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Multiplexer Verilog/VHDL Examples
R
Data Out - DATA_O
VHDL and Verilog Instantiation
VHDL and Verilog Submodules
The data output O provides the data value (1 bit) selected by the control inputs.
Multiplexers are used in various applications. These are often inferred by synthesis tools
when a “case” statement is used (see the following example). Comparators, encoder-
decoders and wide-input combinatorial functions are optimized when they are based on
one level of LUTs and dedicated MUXFX resources of the Virtex-4 FPGA CLBs.
The primitives (MUXF5, MUXF6, and so forth) can be instantiated in VHDL or Verilog
code, to design wide-input functions.
The submodules (MUX_2_1_SUBM, MUX_4_1_SUBM, and so forth) can be instantiated in
VHDL or Verilog code to implement multiplexers. However the corresponding submodule
must be added to the design directory as hierarchical submodule. For example, if a module
is using the MUX_16_1_SUBM, the MUX_16_1_SUBM.vhd file (VHDL code) or
MUX_16_1_SUBM.v file (Verilog code) must be compiled with the design source code. The
submodule code can also be copied into the designer source code.
VHDL and Verilog submodules are available to implement multiplexers up to 32:1. They
illustrate how to design with the MUXFX resources. When synthesis infers the
corresponding MUXFX resource(s), the VHDL or Verilog code is behavioral code (“case”
statement). Otherwise, the equivalent “case” statement is provided in comments and the
correct MUXFX are instantiated. However, most synthesis tools support the inference of all
of the MUXFX. The examples are guidelines for designing other wide-input functions. The
available submodules are:
•
•
•
•
•
The corresponding submodules have to be synthesized with the design. The submodule
MUX_16_1_SUBM is provided as an example in VHDL and Verilog.
VHDL Template
MUX_2_1_SUBM (behavioral code)
MUX_4_1_SUBM
MUX_8_1_SUBM
MUX_16_1_SUBM
MUX_32_1_SUBM
-- Module: MUX_16_1_SUBM
-- Description: Multiplexer 16:1
-- Device: Virtex-4 Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity MUX_16_1_SUBM is
port (
DATA_I: in std_logic_vector (15 downto 0);
SELECT_I: in std_logic_vector (3 downto 0);
www.xilinx.com
Multiplexer Primitives and Verilog/VHDL Examples
229
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