EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 654

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Interfaces
8–10
Stratix Device Handbook, Volume 2
With this XSBI transmitter and receiver block implementation, each XSBI
core requires two fast PLLs. The potential number of XSBI cores per
device corresponds to the number of fast PLLs each Stratix or Stratix GX
device contains.
the number of fast PLLs, and the number of XSBI cores that can be
supported for each Stratix or Stratix GX device.
Note to
(1)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 8–2. Stratix Device XSBI Core Support
Stratix Device
The LVDS channels can go up to 840 Mbps for flip-chip packages and up to
624 Mbps for wire-bond packages. This number includes both high speed and
low speed channels. The high speed LVDS channels can go up to 840 Mbps. The
low speed LVDS channels can go up to 462 Mbps. The High-Speed Differential I/O
Support chapter in the Stratix Device Handbook, Volume 1, and the device pin-outs
on the web (www.altera.com) specify which channels are high and low speed.
Table
8–2:
Tables 8–2
(Receive/Transmit)
Number of LVDS
Channels
116/116
152/156
44/44
66/66
78/78
82/82
90/90
(1)
and
8–3
show the number of LVDS channels,
Number of Fast
PLLs
4
4
4
8
8
8
8
Altera Corporation
Number of XSBI
(Maximum)
Interfaces
2
2
2
4
4
4
4
July 2005