EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 288

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Index–2
Global & Hierarchical Clocking
Global & Regional Clock Connections
Global
Global Clock Network
Global Clocking
Independent Clock Mode
Input/Output
Maximum Input & Output Clock Rates
Maximum Input Clock Rate
Maximum Output Clock Rate
from Side Pins & Fast PLL Outputs
from Top Clock Pins & Enhanced PLL
Clock Mode
for CLK
for PLL
Parameters
Outputs
Clock
Simple Dual-Port Mode
True Dual-Port Mode
(0, 2, 9, 11) Pins in
(1, 3, 8, 10) Pins in
(7..4) & CLK(15..12) Pins in
(1, 2, 3, 4) Pins in
(5, 6, 11, 12) Pins in
2–46
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
2–75
External
4–35
2–86
Packages
Packages
Packages
Packages
Packages
Packages
Packages
Packages
2–74
2–44
I/O
2–73
2–47
2–48
4–77
4–79
4–78
4–80
4–76
4–78
4–83
4–85
Timing
2–85
4–76
Configuration
Control Signals
D
DC Switching
DDR
Device Features
Phase & Delay Shifting
Phase Delay
PLL Clock Networks
Read/Write Clock Mode
Regional Clock
Regional Clock Bus
Regional Clock Network
Spread-Spectrum Clocking
32-Bit IDCODE
and Testing
Data Sources for Configuration
Local Update Mode
Local Update Transition Diagram
Operating Modes
Partial Reconfiguration
Remote Update
Remote Update Transition Diagram
Schemes
SignalTap II Embedded Logic Analyzer
Stratix FPGAs with JRunner
Absolute Maximum Ratings
Bus Hold Parameters
Capacitance
DC & Switching Characteristics
External Timing Parameters
Operating Conditions
Performance
Power Consumption
Recommended Operating Conditions
Double-Data Rate I/O Pins
EP1S10, EP1S20, EP1S25, EP1S30,
EP1S40, EP1S60, EP1S80,
in Simple Dual-Port Mode
External I/O Timing Parameters
2–49
3–7
Stratix Device Handbook, Volume 1
3–5
3–1
4–17
2–96
2–104
Wire-Bond
4–20
2–75
3–3
3–8
3–5
2–79
3–12
4–17
2–73
4–16
Packages
Packages
4–1
2–96
3–7
2–75
1–3
Altera Corporation
2–98
2–111
3–7
4–33
4–1
2–50
3–7
4–1
1–3
3–12
4–81
4–84
4–34
3–11
4–1
3–5