EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 322

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Enhanced PLLs
1–12
Stratix Device Handbook, Volume 2
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
I/O Standard
pair of output pins (four pins total) has dedicated VCC and GND pins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The Quartus II software transfers the NOT
gate in the design into the IOE to implement 180° phase with respect to
the other pin in the pair. The clock output pin pairs support the same I/O
standards as standard output pins (in the top and bottom banks) as well
as LVDS, LVPECL, PCML, HyperTransport
HSTL, and differential SSTL.
enhanced PLL clock pins support. When in single-ended or differential
mode, one power pin supports two differential or four single-ended pins.
Both outputs use the same standards in single-ended mode to maintain
performance. You can also use the external clock output pins as user
output pins if external enhanced PLL clocking is not needed.
The enhanced PLL can also drive out to any regular I/O pin through the
global or regional clock network. The jitter on the output clock is not
guaranteed for this case.
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
Input
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
Table 1–6
shows which I/O standards the
PLLENABLE
TM
v
v
technology, differential
Altera Corporation
EXTCLK
Output
v
v
v
v
v
v
v
v
v
v
v
v
v
v
July 2005