EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 649

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Interfaces
Altera Corporation
July 2005
The following sections discuss XSBI, PCS, XGMII, and XAUI.
XSBI
One of the blocks of 10-Gigabit Ethernet is the XSBI interface. XSBI is the
interface between the PCS and the PMA sublayers of the PHY layer of the
OSI model. XSBI supports two types of PHY layers, LAN PHY and WAN
PHY. The LAN PHY is part of 10GBASE-R, and supports existing
Gigabit Ethernet applications at ten times the bandwidth. The WAN PHY
is part of 10GBASE-W, and supports connections to existing and future
installations of SONET/SDH circuit-switched access equipment.
10GBASE-R is a physical layer implementation that is comprised of the
PCS sublayer, the PMA, and the PMD. 10GBASE-R is based upon
64b/66b data coding. 10GBASE-W is a PHY layer implementation that is
comprised of the PCS sublayer, the WAN interface sublayer (WIS), the
PMA, and the PMD. 10GBASE-W is based on STS-192c/SDH VC-4-64c
encapsulation of 64b/66b encoded data.
construction of these two PHY layers.
Figure 8–3. XSBI Interface for the Two PHY Layers
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
10GBASE-R
Medium
PMA
PMD
PCS
XSBI
MDI
Stratix Device Handbook, Volume 2
10GBASE-W
Figure 8–3
Medium
PMA
PMD
PCS
WIS
shows the
PHY
8–5