EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 49

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

Altera Corporation
3.3 V TTL/CMOS
2.5 V TTL/CMOS
1.8 V TTL/CMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
GTL+
Table 29. EPM7256B Selectable I/O Standard Timing Adder Delays (Part 1 of 2)
I/O Standard
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Input to PIA
Input to global clock and clear
Input to fast input register
All outputs
Parameter
MAX 7000B Programmable Logic Device Data Sheet
Min
-5
Max
–0.1
0.0
0.0
0.0
0.0
0.4
0.3
0.2
0.2
0.6
0.6
0.5
1.3
1.5
1.3
1.1
0.0
1.5
1.3
1.1
1.4
1.1
1.0
0.0
1.4
1.1
1.0
0.0
1.8
1.8
1.7
0.0
Speed Grade
Min
-7
Max
–0.2
0.0
0.0
0.0
0.0
0.6
0.5
0.3
0.3
0.9
0.9
0.8
2.0
2.3
2.0
1.7
0.0
2.3
2.0
1.7
2.1
1.7
1.5
0.0
2.1
1.7
1.5
0.0
2.7
2.7
2.6
0.0
Note (1)
Min
-10
Max
–0.2
0.0
0.0
0.6
0.4
1.2
1.0
2.6
2.2
2.6
2.2
2.2
2.0
2.2
2.0
0.0
0.0
0.8
0.4
1.2
2.6
3.0
0.0
3.0
2.8
0.0
2.8
0.0
3.6
3.6
3.4
0.0
Unit
49
ns
ns
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ns