EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 11

IC MAX 7000 CPLD 512 256-FBGA

EPM7512BFC256-5

Manufacturer Part Number
EPM7512BFC256-5
Description
IC MAX 7000 CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 7000Br
Datasheet

Specifications of EPM7512BFC256-5

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.5ns
Voltage Supply - Internal
2.375 V ~ 2.625 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
212
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 7000B
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
166.67MHz
Propagation Delay Time
5.5ns
Number Of Logic Blocks/elements
32
# I/os (max)
212
Operating Supply Voltage (typ)
2.5V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2361

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0
Figure 4. MAX 7000B Parallel Expanders
Altera Corporation
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
36 Signals
from PIA
Expanders
16 Shared
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000B dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB.
into the LAB. An EEPROM cell controls one input to a two-input AND gate,
which selects a PIA signal to drive into the LAB.
Product-
Product-
Select
Matrix
Select
Matrix
Term
Term
Macrocell
MAX 7000B Programmable Logic Device Data Sheet
Previous
From
Figure 5
shows how the PIA signals are routed
Macrocell
To Next
Preset
Clock
Clear
Preset
Clock
Clear
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic
11

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