EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 25

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

Altera Corporation
Low sustaining current
High sustaining current
Low overdrive current
High overdrive current
Table 12. Bus Hold Parameters
Parameter
V
V
0 V < V
0 V < V
IN
IN
Programmable Pull-Up Resistor
Each MAX 7000B device I/O pin provides an optional programmable
pull-up resistor during user mode. When this feature is enabled for an I/O
pin, the pull-up resistor (typically 50 k¾) weakly holds the output to
V
Bus Hold
Each MAX 7000B device I/O pin provides an optional bus-hold feature.
When this feature is enabled for an I/O pin, the bus-hold circuitry weakly
holds the signal at its last driven state. By holding the last driven state of
the pin until the next input signals is present, the bus-hold feature can
eliminate the need to add external pull-up or pull-down resistors to hold
a signal level when the bus is tri-stated. The bus-hold circuitry also pulls
undriven pins away from the input threshold voltage where noise can
cause unintended high-frequency switching. This feature can be selected
individually for each I/O pin. The bus-hold output will drive no higher
than V
through the input and output buffers in MAX 7000B devices are not
affected by whether the bus-hold feature is enabled or disabled.
The bus-hold circuitry weakly pulls the signal level to the last driven state
through a resistor with a nominal resistance (R
8.5 k¾.
through this resistor and overdrive current that will identify the next
driven input level. This information is provided for each VCCIO voltage
level.
The bus-hold circuitry is active only during user operation. At power-up,
the bus-hold circuit initializes its initial hold value as V
recommended operation conditions. When transitioning from ISP to User
Mode with bus hold enabled, the bus-hold circuit captures the value
present on the pin at the end of programming.
> V
< V
CCIO
Conditions
IL
IH
IN
IN
(max)
(min)
< V
< V
CCIO
level.
Table 12
CCIO
CCIO
to prevent overdriving signals. The propagation delays
gives specific sustaining current that will be driven
Min
–30
30
1.8 V
MAX 7000B Programmable Logic Device Data Sheet
–295
Max
200
VCCIO Level
Min
–50
50
2.5 V
–435
Max
300
BH
Min
–70
70
) of approximately
3.3 V
–680
Max
CC
500
approaches the
Units
μ
μ
μ
μ
A
A
A
A
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