EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 40

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

MAX 7000B Programmable Logic Device Data Sheet
40
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IN
IO
FIN
FIND
SEXP
PEXP
LAD
LAC
IOE
OD1
OD3
ZX1
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 22. EPM7064B Internal Timing Parameters
Symbol
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Programmable delay adder for
fast input
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
slow slew rate = off
V
Output buffer and pad delay
slow slew rate = on
V
Output buffer enable delay
slow slew rate = off
V
Output buffer enable delay
slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(4)
Conditions
Note (1)
Min
0.7
0.4
0.8
1.2
-3
Max
0.3
0.3
0.9
1.0
1.5
0.4
1.4
1.2
0.1
0.9
5.9
1.6
6.6
1.6
0.5
0.2
1.2
1.2
0.7
1.0
1.0
0.7
1.5
Speed Grade
Min
1.1
0.5
0.8
1.2
-5
Max
0.5
0.5
1.3
1.5
2.1
0.6
2.0
1.7
0.2
1.2
6.2
2.2
7.2
2.2
0.6
0.3
1.8
1.7
1.1
1.3
1.3
1.0
2.1
Altera Corporation
Min
1.6
0.9
1.1
1.4
-7
Max
0.7
0.7
2.0
1.5
3.2
0.9
3.1
2.6
0.3
1.8
6.8
3.4
8.4
3.4
0.9
0.5
2.8
2.6
1.6
1.9
1.9
1.4
3.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns