EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 17

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

Altera Corporation
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000B Device
The time required to program a single MAX 7000B device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000B device
can be calculated from the following formula:
where: t
t
t
PROG
VER
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
MAX 7000B Programmable Logic Device Data Sheet
17