EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 35

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

Altera Corporation
t
t
t
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t
t
t
t
t
t
t
t
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t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
FZHSU
FZHH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 18. EPM7032B External Timing Parameters
Input to non-registered
output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of
fast input
Global clock hold time of
fast input
Global clock setup time of
fast input with zero hold
time
Global clock hold time of
fast input with zero hold
time
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
Parameter
Tables 18
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(2)
(2)
(2),
(2)
(2),
(3)
(3)
Conditions
through
(2)
(2)
(2)
32
show MAX 7000B device timing parameters.
MAX 7000B Programmable Logic Device Data Sheet
303.0
303.0
Min
Notes (1)
2.1
0.0
1.0
1.0
2.0
0.0
1.0
1.5
1.5
0.9
0.2
1.0
1.5
1.5
1.5
-3.5
Max
3.5
3.5
2.4
3.6
3.3
3.3
212.8
212.8
Speed Grade
Min
3.0
0.0
1.0
1.0
2.5
0.0
1.0
2.0
2.0
1.3
0.3
1.0
2.0
2.0
2.0
-5.0
Max
5.0
5.0
3.4
5.1
4.7
4.7
142.9
142.9
Min
4.5
0.0
1.5
1.0
3.0
0.0
1.0
3.0
3.0
1.9
0.6
1.0
3.0
3.0
3.0
-7.5
Max
7.5
7.5
5.0
7.6
7.0
7.0
MHz
MHz
Unit
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns