EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 47
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EPM7512BFC256-5
Manufacturer Part Number
EPM7512BFC256-5
Description
IC MAX 7000 CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 7000Br
Datasheet
1.EPM7256BFC256-7.pdf
(66 pages)
Specifications of EPM7512BFC256-5
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.5ns
Voltage Supply - Internal
2.375 V ~ 2.625 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
212
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 7000B
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
166.67MHz
Propagation Delay Time
5.5ns
Number Of Logic Blocks/elements
32
# I/os (max)
212
Operating Supply Voltage (typ)
2.5V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2361
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7512BFC256-5
Manufacturer:
ALTERA
Quantity:
19
Part Number:
EPM7512BFC256-5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7512BFC256-5N
Manufacturer:
ETRON
Quantity:
1 220
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
FZHSU
FZHH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 27. EPM7256B External Timing Parameters
Input to non-registered
output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of
fast input
Global clock hold time for
fast input
Global clock setup time of
fast input with zero hold
time
Global clock hold time of
fast input with zero hold
time
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
Parameter
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(2)
(2)
(2),
(2)
(2),
(3)
(3)
Conditions
(2)
(2)
(2)
MAX 7000B Programmable Logic Device Data Sheet
188.7
188.7
Min
Note (1)
3.3
0.0
1.0
1.0
2.5
0.0
1.0
2.0
2.0
1.4
0.4
1.0
2.0
2.0
2.0
-5
Max
5.0
5.0
3.3
5.2
5.3
5.3
126.6
126.6
Speed Grade
Min
4.8
0.0
1.5
1.0
3.0
0.0
1.0
3.0
3.0
2.0
0.8
1.0
3.0
3.0
3.0
-7
Max
7.5
7.5
5.1
7.9
7.9
7.9
94.3
94.3
Min
6.6
0.0
1.5
1.0
3.0
0.0
1.0
4.0
4.0
2.8
1.0
1.0
4.0
4.0
4.0
-10
Max
10.0
10.0
10.5
10.6
10.6
6.7
MHz
MHz
Unit
47
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns