MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 82

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Registers
B.2.3
B.2.4
82
Table 48. CICBS Bit Descriptions
Note: Writes to this register must be made with extreme caution. In the interest of security, an unlock bit
Intel NetStructure
CICBS- CompactPCI Interface Controller B Status
HCINDEX
Reset
Default Value
Size
Attribute
CICBC- CompactPCI Interface Controller B Command
Register
HCINDEX
Reset
Default Value
Size
Attribute
is included in the CICBS Register. That bit must be set in order to write to this register.
Bit
7
5
4
3
2
1
0
CIC B Present. If this bit is set, there is a CIC B present.
Segment Reset. If set, this bus segment is being held in reset by the PCI
interface device or the CIC.
CICBC Write Enable. If set, the CICBC may be written. If cleared, the
CICBC is read only.
Segment Quiesced (Owner). When in owner mode, if this bit is set, the bus
segment is Quiesced; the arbiter is locked and the bus is idle.
Handover Requested (Drone). When in drone mode, if this bit is set, the
bus owner has requested a handover. This bit is cleared when the handover
is complete. When this bit transitions from 0 to 1, the CICBS flag in the INT
register will be set.
Mode Change. If set, the bus segment interface has changed modes. When
this bit transitions from 0 to 1, the CICBS flag in the INT register will be set.
Owner. If set, this bus segment interface is in owner mode.
RH. If set, this bus segment interface is in a redundant system slot.
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
03h
Not PWROK
0x00
8 bits
RO, W1C, R/W
04h
MRST or Not PWROK
0x00
8 bits
R/W, W1
Description
Access
RO -RH
W1C
R/W
RO
RO
RO
RO
1: Owner
0: Drone
1: RH 0:
Non-RH
Default
X
0
0
0
0