MPCBL5524A1D Intel, MPCBL5524A1D Datasheet
MPCBL5524A1D
Specifications of MPCBL5524A1D
MPCBL5524A1D Summary of contents
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... Intel NetStructure MPCBL5524 High-Performance System Master Processor Board Technical Product Specification February 2006 ® ZT 5524 / Order Number: 273788-009 ...
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... Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ...
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... IPMI ....................................................................................................................... 27 2.4.5 Hot Swap ............................................................................................................... 27 3 Getting Started............................................................................................................................. 28 3.1 Unpacking ........................................................................................................................... 28 3.2 ZT 5524 / MPCBL5524 System Requirements................................................................... 28 3.2.1 Backplane Connectivity ......................................................................................... 28 3.2.2 Electrical and Environmental Requirements .......................................................... 29 3.3 Memory Configuration ........................................................................................................29 ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS ® III Processor ................................................................................ 15 Contents 3 ...
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... Enabling the Watchdog Reset ............................................................... 48 6.4.1.2 Setting the Terminal Count .................................................................... 49 6.4.1.3 Strobing the Watchdog .......................................................................... 49 6.4.2 Watchdog NMI ....................................................................................................... 49 6.4.2.1 Chaining the ISRs .................................................................................. 50 6.4.2.2 Enabling the Watchdog NMI .................................................................. 50 6.4.2.3 NMI Handler........................................................................................... 51 6.4.2.4 Other Watchdog NMI Uses .................................................................... 51 ® 4 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS ...
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... B.1.11 INT- Interrupt Status and Mask Register (E8h)...................................................... 79 B.2 Host Control Function Registers ......................................................................................... 79 B.2.1 CICAS- CompactPCI Interface Controller A Status ............................................... 80 B.2.2 CICAC- CompactPCI Interface Controller A Command......................................... 81 B.2.3 CICBS- CompactPCI Interface Controller B Status ............................................... 82 ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Contents 5 ...
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... Thermal Requirements ....................................................................................................... 86 D.2 Temperature Monitoring ..................................................................................................... 86 E Data Sheet Reference.................................................................................................................. 87 E.1 Chipset................................................................................................................................ 87 E.2 CompactPCI* ...................................................................................................................... 87 E.3 Ethernet .............................................................................................................................. 87 E.4 Intelligent Platform Management Interface (IPMI) .............................................................. 88 E.5 PCI-to-PCI Bridge ............................................................................................................... 88 E.6 Pentium III Processor ......................................................................................................... 88 E.7 I/O Controller ...................................................................................................................... 88 E.8 Thermal Management......................................................................................................... 89 E.9 User Documentation ........................................................................................................... 89 E.10 Video................................................................................................................................... 89 E.11 ZT 5524 / MPCBL5524 Product Page ................................................................................ 89 F Warranty Information ...
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... BIOS POST Codes Bit Description............................................................................................. 75 37 ENUM, WD NMI Status Bit Descriptions .................................................................................... 76 38 Board ID Bit Descriptions............................................................................................................ 76 39 Switch Monitors Bit Descriptions ................................................................................................ 77 40 Ethernet/Geographic Addressing Bit Descriptions...................................................................... 77 41 Video/LED Control Bit Descriptions ............................................................................................ 78 ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Contents 7 ...
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... February 2003 February 2003 November 2002 October 2002 September 2002 ® 8 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Revision Added Section 5.2.3, “IDE HDD Specifications”. 009 Nomenclature changes to add “MPCBL5524”. 008 Modified text in Sections 2.3.7, 3.3, and A.3.2.12. ...
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... Baseboard Management Controller CompactPCI Interface Controller CompactPCI Interface Controller B Command CompactPCI Interface Controller B Status HA Reset Host Control Function Power-On Reset Intelligent Platform Management Interface ISA Watchdog First Stage timeout ISA Watchdog Second Stage timeout Master Reset PCI-to-PCI Peripheral Component Interconnect Push-button Reset ...
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... The ZT 5524 / MPCBL5524 is a 6U, PICMG* 2.16 Version 1.0 compliant CompactPCI* processor board featuring single or dual Low Voltage Intel MPCBL5524 supports one 64-bit CompactPCI bus at 66 MHz or 33 MHz using the Intel BE PCI-to-PCI bridge. When the ZT 5524 / MPCBL5524 is used in conjunction with the Intel ® NetStructure ZT 4901 Bridge Mezzanine board, the two cards can bridge two 64-bit CompactPCI buses at 33 MHz ...
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... CompactPCI Hot Swap Specification, PICMG 2.1, Version 2.0 compliant • CompactPCI Specification, PICMG 2.16, Version 1.0 compliant • Single or dual Low Voltage Intel Pentium III processors (133 MHz FSB) • Integrated 512 KByte ECC L2 cache • Occupies one 6U CompactPCI slot • ...
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... Hot Swap (Blue/Off) — Power/Reset (Green/Amber/Off) — Ethernet C: •10/100 (Off/Green) •Link (Green) •Activity (Flashing Green) — Ethernet A and B: •10/100/1000 (Off/Green/Amber) •Link (Green) •Activity (Flashing Green) • Six SMBuses (Local) ® 12 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS ...
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... Power/Reset LED User LED 1 1 Ethernet A Ethernet B USB Abort Request/Alarm Cutoff Switch CPU Reset Switch Hotswap LED ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Ejector Handle Ejector Handle Introduction IDE Activity LED User LED 2 2 Status LED 13 ...
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... J1/J2 (Second Slot) *Other names and brands may be claimed as the property of others. ® 14 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Low Voltage Intel ® Low Voltage Intel Pentium ® III 933 MHz Processor 133 MHz System Bus (1066 MB/s) Intel ® ...
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... Intel Pentium The ZT 5524 / MPCBL5524 features either one or two Low Voltage (LV) Intel Pentium III 512 KByte processor(s). The Pentium III processor is a small, highly integrated assembly containing an Intel Pentium processor and its immediate system-level support. The Pentium III processor includes 32 KBytes of code and data cache (L1 cache), a secondary 512 KByte cache (ECC L2 cache), and the core logic required to bridge the processor to the standard system buses ...
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... CompactPCI Bus Interface The ZT 5524 / MPCBL5524 processor board uses the CNB30 chipset and the Intel 21154-BE PCI- PCI Bridge to support 32-bit and 64-bit CompactPCI interfaces. ZT 5524 / MPCBL5524 supports up to two 64-bit CompactPCI buses at 33 MHz in RH Mode and either 33 MHz or 66 MHz in Standard Mode ...
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... CompactPCI connectors. 2.3.5 Baseboard Management Controller The ZT 5524 / MPCBL5524 includes a Baseboard Management Controller (BMC) chip from Intel. The BMC subsystem monitors, controls, and performs remote diagnostics for many on- and off- board functions through six IPMI compliant system management bus interfaces. The BMC monitors system sensors for system management events, such as overtemperature, out- of-range voltages, fan failures, etc ...
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... BMC Fault For more information about Intel’s High Availability architecture and development of Redundant Host drivers, refer to the Redundant Host Software Development Kit for Intel NetStructure CompactPCI System Master Processor Boards Software Manual. See Documentation.” for information on locating this document. ...
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... Redundant Host (RH) functionality, dual Fibre Channel, dual 64/ 66 PMC, and access to a second CompactPCI bus segment for bridging. Intel designed the ZT 4901 to be used as a Redundant System Master for one or two bus segments, a CompactPCI Bridge to a second CompactPCI bus segment standalone, add-on peripheral mezzanine to the ZT 5524 / MPCBL5524 ...
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... Interrupt controller features include support for: • Level-triggered and edge-triggered inputs • Individual input masking • Fixed and rotating priorities Interrupt sources include: ® 20 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS for more information. Timer,”for more information. Appendix E, “Chipset.” ...
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... The ZT 5524 / MPCBL5524 supports booting from a USB CD-ROM or floppy device. Refer to the ZT 5524 / MPCBL5524 Compatibility Report available on the Intel website for a complete list of validated CD-ROM and floppy drives. A link to this website is available in the section “ZT 5524 / MPCBL5524 Product Page.” ...
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... Note: The recommended method of accessing the date in systems with Intel processor boards is indirectly from the real time clock via the BIOS. The BIOS on Intel processor boards contains a century checking and maintenance feature. This feature checks the two least significant digits of the year stored in the real time clock during each BIOS request (INT 1Ah) to read the date and, if less than ® ...
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... MHz, giving it a theoretical bandwidth of 133 MB/s. The 69000 provides support for display resolutions up to 1024 x 768. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS COM1 via RJ-45 connector J9 COM1 and COM2 via RPIO connector J5 Appendix A, “ ...
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... Ethernet Interfaces The ZT 5524 / MPCBL5524 provides two 10/100/1000Base-T Ethernet channels (ENET A and ENET B) through the Intel status LEDs to indicate the status of each channel, are available on the faceplate via connector J7. Ethernet channels A and B can be directed through the BIOS setup to the RPIO connector J3. ...
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... Green = healthy • Amber = needs service 2.3.26 Rear-Panel I/O The ZT 5524 / MPCBL5524 transitions the following I/O signals through CompactPCI connector rear-panel transition (RPIO) board such as the Intel NetStructure Transition Board: • Floppy • Two serial ports (COM1 and COM2) • ...
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... Connectors.” 2.4 Software This section explains key software components. 2.4.1 BIOS The Intel NetStructure Embedded BIOS (AMI core) is loaded in flash on board the ZT 5524 / MPCBL5524. The BIOS is user-configurable to boot an operating system from one of the following locations: • Local flash memory • ...
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... Specification, PICMG 2.1, Version 2.0, the ZT 5524 / MPCBL5524 supports hosting hot swap peripherals in a powered system. CompactPCI Hot Swap Specification. Intel’s Hot Swap Kit provides software that collaborates with the operating system to provide hot swap support for CompactPCI. For more information, refer to the Intel NetStructure Software Manual. ...
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... Unpacking Check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and Intel. Retain the shipping carton and packing material for inspection by the carrier. Obtain authorization before returning any product to Intel. Refer to page 90 for assistance information. ...
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... MByte to a maximum of 1 GByte (single DIMM socket GBytes (four DIMM sockets) of 133 MHz SDRAM memory. Refer to the ZT 5524 / MPCBL5524 Compatibility Report, available on the Intel website, for a complete list of compatible memory types. A link to this website is available in Figure 3, “Memory Address Map Example” on page 30 ZT 5524 / MPCBL5524 ...
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... FEC00000 - FEC00FFFh Top of Memory - FEBFFFFFh 00100000h -Top of Memory E0000h - FFFFFh C8000h - D7FFFh C0000h - C7FFFh A0000h - BFFFFh ® 30 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS System BIOS/On-Board Flash Reserved Local APIC Reserved I/O APIC I/O APIC PCI System Memory ...
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... Table 1. I/O Address Map (Sheet ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS General Purpose Chipset F50-F58h Power Management Data Register CD7h Power Management Index Register CD6h Miscellaneous Control Registers C6Fh ISA Wait Register C6Ch General Purpose Registers ...
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... The ZT 5524 / MPCBL5524’s BIOS is fully IBM VGA and VESA compatible. The BIOS is automatically installed during system initialization and is mapped to the standard C0000 to C7FFFh VGA BIOS memory space. ® 32 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS NMI Enable Register 70h NMI Status Register ...
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... BIOS Configuration Overview This topic presents a brief introduction to the Intel NetStructure Embedded BIOS. For more detailed information about the BIOS and other utilities, see the Intel NetStructure Embedded BIOS (AMI Core) Software Manual. A link to this document is available in Documentation.” ...
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... The Console Redirection option in the BIOS can be overridden by hardware switch 3-1. Console Redirection is enabled by default in the BIOS but is disabled by default by the hardware switch. See the Intel NetStructure Embedded BIOS (AMI Core) Software Manual for more information about console redirection. A link to this document is available in Documentation.” ...
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... Installing the Operating System For more detailed information about your operating system, refer to the documentation provided by the operating system vendor and to the ZT 5524 / MPCBL5524 Product Page on the Intel website (URL listed in Appendix E, “ZT 5524 / MPCBL5524 Product Page” To install the operating system 1 ...
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... USER LED 1 ON (AMBER) cli in al, E5h and al, F3h or al, 04h out E5h, al sti ; set LED OFF cli ® 36 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Figure 1 on page 13). The user LEDs are software programmable State Amber Green Both Off Amber ...
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... Code for Modifying Bits of User LED 1 (Sheet Code in al, E5h and al, F3h out E5h, al sti ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description ; read current state ; set bit 1 to turn off LED ; output new value for register ; re-enable interrupts ...
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... Master/Slave Drive Select Software Configured Video Select ® 38 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Chapter 3, “BIOS Configuration shows the ZT 5524 / MPCBL5524’s switch settings as shipped from the provides a blank switch layout; print this figure and use it to document ...
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... Figure 5. Factory Default Switch Configuration SW3 SW5 SW6 Figure 6. Customer Switch Configuration SW3 SW5 SW6 ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS SW1 SW2 SW4 SW1 SW2 SW4 Configuration 39 ...
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... This switch designates an IDE drive attached to onboard IDE connector J19 as a master or slave IDE device. Opening SW3-4 selects the drive as a master device. Closing SW3-4 assigns the drive as a slave device. Factory default is closed. ® 40 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Figure 1, “ZT 5524 / MPCBL5524 Faceplate” on page 13. page ...
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... SW4-3 (Reserved) The function of this switch is reserved and should not be altered from its factory default setting (open). ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS “Flash Utility Program” on page bit of the Flash Control register (Port 78h, bit 1) must also be properly set Table 34 on page 73) ...
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... SW5-4, SW6-1 (Reserved) The functions of these switches are reserved and should not be altered from their factory default settings (open). ® 42 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS SW6-2 Function Open Normal operation– battery backed CMOS (Default) ...
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... Function Open (Default) Drone PCI Reset Enabled Closed Ignore PCI Reset 4.2.14 SW6-4 (Reserved) The function of this switch is reserved and should not be altered from its factory default setting (open). ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Configuration 43 ...
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... The ZT 5524 / MPCBL5524 primary IDE channel is directed to IDE connector J19. Connector J19 is used to connect to a locally mounted 2.5 inch, low-profile hard drive. Primary IDE signals are also routed to the J17 mezzanine board interface. ® 44 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Appendix E, “Chipset.” Appendix A, “ZT 5524 / 5 ...
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... Width x Depth) Weight Disk characteristics for Cylinder-Head-Sector (CHS) mode: Characteristic Formatted Capacity Number of Heads Number of Cylinders (User) Number of Sectors in CHS Mode (User) ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Value 35,968 78,140,160 512 48/50 RLL 2.42 K tracks/mm (61,500 TPI) 23 ...
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... PC-AT legacy addresses of 1F0h-1F7h, with 3F6h and interrupt IRQ14 for the primary channel. The secondary channel uses I/O addresses 170h-177h, 376h, and interrupt IRQ15. No memory addresses are used. ® 46 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 31). The default mode is compatibility mode, which means that the Table 1, “I/O ...
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... Watchdog register. This resets the timer. If the timer is not reset within the timeout interval, the watchdog timer drives an NMI followed by RST 250 ms later. The NMI gives the application 250 ms to perform essential tasks before the hardware is reset. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Port 79h Control ...
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... WdValue; WdValue = inb(WD_CSR_IO_ADDRESS); WdValue |= WD_RESET_EN_BIT_SET; local outb(WD_CSR_IO_ADDRESS,WdValue); // register. } ® 48 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Appendix B, “Watchdog (79h)” B for more information. 0x20 // Holds watchdog register values Read the current contents of the //watchdog register. // Assert the enable bit in the //copy ...
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... The code for performing the essential tasks is included in an interrupt service routine (ISR) • The ISR is chained to the existing NMI ISR • The watchdog NMI is enabled ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Watchdog Timer 0x79 // IO address of the watchdog 0x07 // Bit mask for terminal count bits ...
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... EnableWatchdogNMI(void){ unsigned char WdValue; WdValue = inb(WD_CSR_IO_ADDRESS); WdValue |= WD_NMI_EN_BIT_SET; copy. outb(WD_CSR_IO_ADDRESS,WdValue); } ® 50 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS // Save the old // Install the new. 0x10 // Holds watchdog register values Read the current contents of the //watchdog register. // Assert the enable bit in the local // Assert the enable in the watchdog // register ...
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... Other Watchdog NMI Uses The watchdog NMI feature can be used independently of the watchdog reset feature. Code for checking the bit is provided in the ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS // Bit that indicates a NMI occurred, set TripAlarm() ...
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... EPROM is removed for any reason, ensure that it is correctly oriented when reinstalled. Orient the beveled corner of the BIOS Recovery module as shown in the “BIOS Recovery Socket Location” figure below. Table 13. BIOS Recovery Socket Location ® 52 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS BIOS Recovery Module 7 ...
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... To reprogram the BIOS on the ZT 5524 / MPCBL5524, use the following syntax at a DOS prompt: FLASH /b BIOS.XXX where BIOS.XXX is the BIOS image for the ZT 5524 / MPCBL5524. See the Intel NetStructure Embedded BIOS (AMI Core) Software Manual for more information on the Flash utility. A link to ...
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... System Monitoring and Alarms The ZT 5524 / MPCBL5524 performs system monitoring and alarming functions using the flexible, industry standard, Intelligent Platform Management Interface (IPMI). The ZT 5524 / MPCBL5524 comes equipped with an on-board Baseboard Management Controller (BMC) chip, IPMI and IPMB J-connector pinouts, and IPMI v1.5 firmware already installed on the board. Some of the functions available on this board through the IPMI interface include: • ...
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... ADM1026 RPIO FRU Device Mezzanine Card FRU Device Mezzanine RPIO Card FRU Device ADM1026 Mezzanine 10/100 Ethernet Controller C ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS System Monitoring and Alarms Set by external TCO N/A software Master Controller Slave ...
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... Supply Voltage, Vcc: Supply Voltage, Vcc3: Supply Voltage, AUX +: Storage Temperature: Non-Condensing Relative Humidity: Ethernet Cable Length ® 56 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS “DC Operating Characteristics” topic in this appendix for operating Limit 5 -40° to +85° C < ...
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... The heat sink requires 250 LFM (linear feet per minute) of airflow. The maximum power dissipation of each CPU is 13.2 W. Caution: External airflow must be provided at all times during operation to avoid damaging the CPU modules. Intel strongly recommends use of a fan tray below the card rack to supply the external airflow. A.1.2 DC Operating Characteristics Table 16 ...
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... Board Width Board Height: Board Weight: Figure 8. ZT 5524 / MPCBL5524 Board Dimensions ® 58 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Figure 8 and are outlined below. 160 mm (6.24 in) 233.35 mm (9.1 in) 34.80 mm (1.37 in) typ., measuring from the tallest secondary side component to the tallest primary side component Dual processors: ...
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... SDRAM Connector (DIMM) J17, page 68 I/O Mezzanine Interface (190-pin female vertical) J18, page 70 ISP Programming (10-pin female vertical) J19, page 70 On-board EIDE Interface (50-pin female vertical) ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 60, the ZT 5524 / MPCBL5524 includes Function Specifications 59 ...
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... Specifications Figure 9. Connector Locations J6 - USB J12 - Hot Swap Ejector Switch J1 CompactPCI Bus Figure 10. Backplane Connectors Pin Locations ® 60 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS J8 - Keyboard/Mouse J10 - Video J7 - Ethernet Serial J17 - I/O Mezzanine Interface J2 J3 Ethernet A, B J11 - Ethernet C ...
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... AD[30] 6 REQ INTA Pin A = long pins NOTE: Row F GND pins are long length standard for CompactPCI. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS B C REQ64# ENUM# 3.3V 5V V(I/O) AD[0] AD[4] AD[3] 5V GND 3.3V AD[6] AD[9] AD[8] GND ...
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... AD[45] 10 AD[49] 9 AD[52] 8 AD[56] 7 AD[59] 6 AD[63] 5 C/BE[5]# 4 V(I/O) 3 CLK4 2 CLK2 1 CLK1 Pin # A ® 62 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS for pin placement GA3 GA2 GA1 GND NC SMB DATA SMB CLK NC NC GND GND PRST# REQ7# NC DEG# GND ...
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... 110-pin mm, female connector providing rear-panel access to the following: • IDE • COM port • Ethernet LED • Video • Keyboard/Mouse • Floppy • RPIO Eject • USB ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS LPA_DA- GND LPA_DC+ LPA_DB- GND LPA_DD+ LPB_DA- GND LPB_DC+ LPB_DB- ...
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... MTR1- 8 DENSL 7 CS1S- 6 PWRGD 5 DDRQ 4 DD14 3 DD3 2 DD9 1 PBRST- Pin # A ® 64 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS for pin placement USB0- SW-5V USB1+ GND GND GND GND H-SYNC GND SW-5V GND SW-5V GND V-SYNC GND RESV RPIO_PRESENT# ...
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... Addressing (E4h)” on page 77 J Table 24. 7 Ethernet Connectors Pinout Pin# Function 1 MDIO0 2 MDIO0- 3 MDIO1 4 MDIO2 5 MDIO2- 6 MDIO1- 7 MDIO3 8 MDIO3- ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Figure 1, “ZT 5524 / MPCBL5524 Faceplate” on for more information. Specifications “Ethernet/Geographic 65 ...
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... COM1 interface signals are also directed out rear-panel I/O connector J5. See the following table for pin definitions. Table 26. J9 COM1 Serial Port Pinout Pin# Function 1 RTS 2 DTR 3 TXD 4 GND 5 GND 6 RXD 7 DSR 8 CTS ® 66 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 13. ...
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... J12 is a 3-pin, vertical, 1.25 mm (.049 in) surface-mount connector connecting the hot swap switch to the board’s lower ejector mechanism. This switch is tied to logic on the ZT 5524 / MPCBL5524 to sense a board extraction or insertion. See the following table for pin definitions. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Pin # Signal ...
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... B3_INTAO- 10 B3_INTCO- 11 B3_INTBO- 12 B3_INTD- 13 B1_PAD31 14 B1_PAD30 15 B1_PAD29 16 B1_PAD28 17 B1_PAD27 18 B1_PAD26 19 B1_PAD25 ® 68 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Pin Signal Name Pin Signal Name 51 B1_PAD13 101 B1_PAD43 52 B1_PAD14 102 B1_PAD44 53 B1_PAD10 103 B1_PAD41 54 B1_PAD12 104 B1_PAD42 55 B1_PAD9 ...
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... GND 41 B1_DEVSEL- 42 IOXCLKB 43 GND 44 GND 45 IOXCLKA 46 B1_CBE-1 47 GND 48 B1_LOCK- 49 B1_PAD15 50 B1_SERR- ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Pin Signal Name Pin Signal Name 70 B1_REQ-2 120 S2_ENUM- 71 B1_GNT-3 121 MEZ_INTD- 72 B1_REQ-3 122 CSEL2 73 B1_M66EN 123 PDASP 74 B1_ACK64- ...
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... EIDE interface. See the following table for pin definitions. Table 32. J19 EIDE Interface Pinout (Sheet Pin# Signal 1 RST- 2 GND 3 DDP7 4 DDP8 5 DDP6 6 DDP9 7 DDP5 8 DDP10 9 DDP4 10 DDP11 11 DDP3 12 DDP12 13 DDP2 14 DDP13 15 DDP1 16 DDP14 17 DDP0 18 DDP15 ® 70 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS ...
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... GND 25 PDIOR- 26 GND 27 PDIORDY 28 CSEL 29 PDACK- 30 GND 31 IRQ14 1 32 IOCS16- 33 DAP1 34 PDIAG 35 DAP0 36 DAP2 37 CS1P- 38 CS3P- 39 PDASP 40 CS3P- 41 VCC 42 VCC 43 GND NOTE: IOCS16- has 10kΩ pullup to VCC3 (+3.3V) ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Specifications 71 ...
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... Flash Control (78h) I/O Address Default Value Size Attribute Note: This register is reset to 00h on init or reset. The BIOS resides in page 000. ® 72 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Register Name Default Value 0x00 0x00 0x00 0x00 0x00 ...
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... Reserved. These bits are reserved and should be written as logical 0s when this register is modified. B.1.2 Watchdog (79h) I/O Address Default Value Size Attribute ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description page 41). If the BIOS Recovery Module Chapter 7, “BIOS Recovery,” 79h 0x00 ...
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... The Stage 2 Monitor bit is set to 1 and stays high until set software Reset action occurs approximately 250 ms after NMI Power-Up Value: 0 Value After Timeout: 0 (doesn’t re-arm) A hard reset sets this bit to 0. ® 74 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description ...
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... PCB. The Port 80 bits report the BIOS POST (diagnostic) codes. These LEDs may not be visible if a “hot-swap shield” is installed on the bottom side on the PCB. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 100 = 32 s 101 = 64 s 110 = 128 s ...
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... BIOS. These bits should be written as logical 0s when this register is modified. B.1.6 Switch Monitors (E3h) Address Offset Default Value Size Attribute ® 76 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 0xE1h 0x00 8 bits RO Description E2h 0x00 8 bits ...
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... Bit 0 = GA0; Bit 1 = GA1; Bit 2 = GA2; Bit 3 = GA3; Bit 4 = GA4. A logical 0 indicates that the corresponding GA pin is open. A logical 1 indicates that the corresponding GA pin is low (GND). ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description page 41). A logical 0 means that the flash is write-protected by SW4-1; a logical 1 ...
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... Host Control Function Data Pointer - This register provides the address offset for the HCDATA 2:0 registers. This is the number listed in the HCINDEX Offset column in the Host Control Function Register table (see ® 78 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS E5h 0x00 8 bits WO ...
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... For added register security, an index and data register pair is used to access the Host Control Function (HCF) Registers. Each of these registers is addressed by the value in the HCINDEX Register at I/O Address E6h. Data access is provided via the HCDATA Register. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS E7h PCIRST ...
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... CICAS flag in the INT register will be set. 1 Owner. If set, this bus segment interface is in owner mode 0 RH. If set, this bus segment interface Redundant Host slot ® 80 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Register Name Reserved CompactPCI Interface Controller A Status CompactPCI Interface Controller A ...
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... Backplane Bus Segment RESET MASK. When this bit is 1, the PCI RST the backplane is masked and will not be asserted when in Owner Mode. The RST# will not be asserted in Drone Mode even if this bit is cleared. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 02h Not PWROK or MRST 0x00 ...
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... Note: Writes to this register must be made with extreme caution. In the interest of security, an unlock bit is included in the CICBS Register. That bit must be set in order to write to this register. ® 82 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS 03h Not PWROK 0x00 ...
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... Backplane Bus Segment RESET MASK. When this bit is 1, the PCI RST the backplane is masked and will not be asserted when in Owner Mode. The RST# will not be asserted in Drone Mode even if this bit is cleared. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Description System Registers Access ...
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... When the System Reset button (SW1) on the faceplate is pressed, the ZT 5524 / MPCBL5524 resets itself and drives PCIRST on both CompactPCI buses. Sources for push-button reset include: • Faceplate push-button Reset switch (SW1) • Programmable watchdog timer ® 84 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS C ...
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... An NMI push button may be available on the optional RPIO transition board (such as the ZT 4807 Rear-Panel Transition Board). Pressing this button causes the ZT 5524 / MPCBL5524 to generate a non-maskable interrupt. ® Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS Figure 1, “ZT 5524 / MPCBL5524 Faceplate” on page Chapter ...
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... C. The maximum ambient air temperature assumes an airflow of 250 linear feet per minute past the heat sinks. Caution: External airflow must be provided at all times during operation to avoid damaging the CPU. Intel strongly recommends use of a fan tray below the card rack to supply the external airflow. ...
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... Ethernet PCI Controller. Refer to the Intel 82546EB Dual Port Gigabit Ethernet Controller data sheet for more information. The data sheet is in HTML format and available online at: http://www.intel.com/design/network/products/lan/controllers/82546.htm 10/100Base-T Ethernet is implemented on the ZT 5524 / MPCBL5524 via the Intel 82550 Fast Ethernet Multifunction Controller. More information is available online at: http://www.intel.com/design/network/products/lan/controllers/82550.htm ® ...
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... Interface, including the Intelligent Platform Management Interface v1.5 Specification and the Intelligent Platform Management Interface Implementer’s Guide: http://developer.intel.com/design/servers/ipmi/spec.htm E.5 PCI-to-PCI Bridge For more information about the Intel 21154-BE PCI-to-PCI bridges used on the ZT 5524 / MPCBL5524 CPU, visit the Intel website addressed below. http://developer.intel.com/design/bridge/ E.6 Pentium III Processor ...
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... Management Controller, see the manufacturer’s website at: http://products.analog.com/products/info.asp?product=ADM1026 E.9 User Documentation The latest Intel NetStructure ® product information and manuals are available on the Intel NetStructure website. BIOS and driver updates are also available from this site. http://developer.intel.com/design/network/products/cbp/linecard.htm. E.10 Video For more information on the Chips and Technologies* 69000 HiQVideo Accelerator with Integrated Memory, refer to the 69000 HiQVideo Accelerator with Integrated Memory data sheet ...
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... This warranty does not cover replacement of products damaged by abuse, accident, misuse, neglect, alteration, repair, disaster, improper installation or improper testing. If the product is found to be otherwise defective, Intel, at its option, will replace or repair the product at no charge except as set forth below, provided that you deliver the product along with a return material authorization (RMA) number (see below) either to the company from whom you purchased Intel ...
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... Return Material Authorization (RMA) credit requests e-mail address: Direct Return Authorization (DRA) repair requests e-mail address: DRA on-line form: Intel Business Link (IBL): Telephone No.: 1-800-INTEL4U or 480-554-4904 Office Hours: Monday - Friday 0700-1700 MST Winter / PST Summer F.1.3 For EMEA Return Material Authorization (RMA) e-mail address - ...
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... If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/RMA number to place on the outer package of the product. Intel cannot accept any product without a DRA/RMA number on the package. Limitation of Liability and Remedies ...
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... Intel NetStructure product for service. G.1 Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information. G.2 Sales Assistance If you have a sales question, please contact your local Intel ® NetStructure or the Regional Sales Office for your area ...
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... IEC 61000 4-3 (1995) IEC 61000 4-4 (1995) IEC 61000 4-6 (1996) ® 94 Intel NetStructure ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS UL Safety of Information Technology Equipment, including Electrical Business Equipment IEC 950 and UL 1950 (UL file # E179737) AC Line Conducted Emissions Test ...
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... FCC 47 CFR Part 15, Subpart B, Class A of the FCC Rules. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. Intel NetStructure system RFI and Radiated Immunity tests were conducted with a specific configuration representing an anticipated general application ...