MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 40

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Configuration
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
40
Table 5.
Intel NetStructure
Switch Descriptions
The following topics present the switches in numerical order and provide a detailed description of
each switch. Multiple-position switches are identified in the form SWx-N, where x is the switch
number and -N is the switch position (for example, SW3-2 means “switch number 3, position 2”).
SW1 (CPU Reset)
SW1 is a push button on the ZT 5524 / MPCBL5524’s faceplate. When pressed with a short pulse,
SW1 issues a Reset Request to the CPU. Pressing on the switch for 2 seconds forces a hard CPU
reset. For a diagram of the faceplate, see
SW2 (Abort Request)
SW2 is a push button on the ZT 5524 / MPCBL5524’s faceplate. When pressed, SW2 issues an
Abort Request (NMI) to the CPU. For a diagram of the faceplate, see
MPCBL5524 Faceplate” on page
SW3-1 (Console Redirection)
Close this switch to enable console redirection (see
by the user’s software through the Switch Monitors register (Port E3h Bit 0) Console Redirection
Enable bit to provide user-configurable features (see
reads back a 0; when closed it reads back a 1. Factory default is open.
SW3-1 Settings
SW3-2, SW3-3 (Software Configured)
These switches are used to provide configuration information to the user’s software. The Software
Configuration bits of the Switch Monitors register (Port E3h Bits 1-2) monitors the status of SW3
segments as listed below (see
reads back a 1. The switch segments correspond to register bits as follows:
SW3-4 (Master/Slave Drive Select)
This switch designates an IDE drive attached to onboard IDE connector J19 as a master or slave
IDE device. Opening SW3-4 selects the drive as a master device. Closing SW3-4 assigns the drive
as a slave device. Factory default is closed.
SW3-1
Open (Default)
Closed
•
•
SW3-2 = Bit 1
SW3-3 = Bit 2
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Reading
1
0
Function
Console Redirection Disabled
Console Redirection Enabled
Table 39 on page
13.
Figure 1, “ZT 5524 / MPCBL5524 Faceplate” on page
77). An open switch reads back a 0; a closed switch
page
Table 39 on page
34). The status of this switch is monitored
Figure 1, “ZT 5524 /
77). When open, this switch
13.