MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 77

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B.1.7
Intel NetStructure
Table 39. Switch Monitors Bit Descriptions
Table 40. Ethernet/Geographic Addressing Bit Descriptions
Ethernet/Geographic Addressing (E4h)
Address Offset
Default Value
Size
Attribute
5:3
2:1
4:0
Bit
®
Bit
7
6
0
7
6
5
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Flash Write-Protect Status. This bit corresponds to the status of Flash Write Protect/Write Enable
switch SW4-1 (see
means that the flash is not write-protected by SW4-1.
Boot Source Monitoring. This bit allows software to monitor the boot source as selected by SW4-2
(see
When SW4-2 is open (boot from the BIOS contained in on-board flash), this bit reads back a 1.
Reserved. These bits are reserved and should not be modified by the user.
Software Configuration. These bits are used to provide configuration information to the user’s
software by monitoring the status of the Software Configuration switch SW3 (see
switch reads back a 0; a closed switch reads back a 1. The bits correspond to switch segments as
follows:
Bit 1 = SW3-2; Bit 2 = SW3-3
Console Redirection Enable: This bit reads the status of switch SW3-1 (see
means that SW3-1 is open and console redirection is disabled. A logical 1 means SW4-4 is closed
and console redirection is enabled
Reserved. This bit is reserved and should not be modified by the user.
Ethernet B Front/Rear Select. This bit toggles Ethernet channel 2 (Ethernet B) connection between
the faceplate and the backplane. This bit can be set in the BIOS setup screen. When this bit is set to
logical 0, Ethernet Channel 2 is connected to the Ethernet faceplate connector J7 (see
When this bit is set to logical 1, Ethernet Channel 2 is connected to J3 (see
panel.
Ethernet A Front/Rear Select. This bit toggles Ethernet channel 1 (Ethernet A) connection between
the faceplate and the backplane. This bit can be set in the BIOS setup screen. When this bit is set to
logical 0, Ethernet channel 1 is connected to the Ethernet faceplate connector J7. When this bit is set
to logical 1, Ethernet channel 1 is connected to J3 on the rear panel.
Geographic Addressing. CompactPCI defines several signal additions to the PCI specification. One
of these is GA[4..0], used for geographic addressing on the backplane. Geographic addressing
uniquely differentiates each board based on the physical slot into which it has been inserted. Each
backplane connector in a CompactPCI system has a unique encoding for GA[4..0]. See the
CompactPCI Specification, PICMG 2.0 R3.0 for more information on geographic addressing. The bits
correspond to signals as follows:
Bit 0 = GA0; Bit 1 = GA1; Bit 2 = GA2; Bit 3 = GA3; Bit 4 = GA4.
A logical 0 indicates that the corresponding GA pin is open. A logical 1 indicates that the
corresponding GA pin is low (GND).
page
41). When SW4-2 is closed (boot from BIOS Recovery socket U42), this bit reads back a 0.
page
E4h
0x00
8 bits
R/W
41). A logical 0 means that the flash is write-protected by SW4-1; a logical 1
Description
Description
page
System Registers
page
page
63) on the rear
40). A logical 0
40). An open
page
65).
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