MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 15

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.3.1
2.3.2
2.3.2.1
2.3.2.2
Intel NetStructure
Intel
The ZT 5524 / MPCBL5524 features either one or two Low Voltage (LV) Intel Pentium III
512 KByte processor(s). The Pentium III processor is a small, highly integrated assembly
containing an Intel Pentium processor and its immediate system-level support. The Pentium III
processor includes 32 KBytes of code and data cache (L1 cache), a secondary 512 KByte cache
(ECC L2 cache), and the core logic required to bridge the processor to the standard system buses. It
also features a 133MHz system bus frequency.
Appendix E, “Pentium III Processor,”
Chipset
The ZT 5524 / MPCBL5524 incorporates the ServerWorks* Champion* LE-T chipset. The
Champion LE-T chipset consists of the ServerWorks Champion North Bridge (CNB30LE-T) and
the ServerWorks Champion South Bridge (CSB5) chips.
ServerWorks* Champion North Bridge (CNB30LE-T)
The CNB30LE-T provides an optimized, integrated DRAM controller, bus-control signals, address
paths, and data paths for transfers between the processor’s host bus, the PCI bus, and main
memory. The CNB30LE-T also features:
ServerWorks Champion South Bridge (CSB5)
The ZT 5524 / MPCBL5524 I/O subsystem is based on the CSB5. The CSB5 is a multifunctional
PCI device implementing the PCI-to-ISA bridge, PCI IDE functionality, USB host/hub
functionality, and enhanced power management. The CSB5 South Bridge features:
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Processor interface control
Data buffering
Power management functions
SMBus support for desktop management functions
Support for system management mode (SMM)
Glueless Serial interface with CSB5
Multifunctional PCI-to-LPC Address / Data bridge
PCI Slave, PCI Arbiter, and PCI Master
LPC bus support and LPC Arbiter
One 8253 Counter/Timer
Client Management
Support for the PCI bus at 33 MHz
Support for PCI Rev 2.1 Specification
Integrated dual-channel enhanced IDE interface
Enhanced DMA controller
Interrupt controller based on 82C59
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
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Pentium
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III Processor
contains a link to the datasheet for this device.
Introduction
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