MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 51

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MPCBL5524A1D

Manufacturer Part Number
MPCBL5524A1D
Description
Manufacturer
Intel
Datasheet

Specifications of MPCBL5524A1D

Lead Free Status / Rohs Status
Supplier Unconfirmed
6.4.2.3
6.4.2.4
Intel NetStructure
NMI Handler
Because the NMI may have originated from another source such as a RAM Error Correction Code
(ECC) error, the NMI handler cannot assume that the NMI occurred due to a watchdog time out.
Therefore, the NMI handler must check the Watchdog Status register before taking watchdog-
related emergency action. When the NMI handler completes handling the emergency, it invokes the
original NMI handler. The code to do this might look like the following:
#define WD_NMI_DETECT_BIT_SET0x40
void WatchdogIsr(void){
}
Other Watchdog NMI Uses
The watchdog NMI feature can be used independently of the watchdog reset feature. Code for
checking the bit is provided in the
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
//
if(inb(WD_CSR_IO_ADDRESS) & WD_NMI_DETECT_BIT_SET){
// Did the watchdog cause the NMI?
//
}
_chain_intr(OldNMIIsr);
TripAlarm();
TurnOffTheGas();
“NMI Handler”
//
//
//
topic above.
// Bit that indicates a NMI occurred, set.
//
// Take care of essential tasks.
//
//
//
// Invoke the originally installed ISR.
Watchdog Timer
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