MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 17

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.3.5
2.3.6
Intel NetStructure
Note: See
Special features of the 21154-BE include:
A link to the datasheet for this device is listed in
Appendix A, “ZT 5524 / MPCBL5524 Connectors”
CompactPCI connectors.
Baseboard Management Controller
The ZT 5524 / MPCBL5524 includes a Baseboard Management Controller (BMC) chip from Intel.
The BMC subsystem monitors, controls, and performs remote diagnostics for many on- and off-
board functions through six IPMI compliant system management bus interfaces.
The BMC monitors system sensors for system management events, such as overtemperature, out-
of-range voltages, fan failures, etc., and logs any occurrences in its non-volatile System Event Log
(SEL). The BMC also provides the interface to the sensors and SEL so system management
software can poll and retrieve the present status of the system.
The ZT 5524 / MPCBL5524 is compliant with standard Intelligent Platform Management Interface
v1.5 Specification functionality. Optional IPMI functionality addressed in the specification is not
supported. See
information.
Redundant Host Operation
Intel’s High Availability architecture features two Redundant Host ZT 5524 / MPCBL5524
processor boards with ZT 4901 Bridge Mezzanine boards in a single PICMG 2.16 compliant High
Availability enclosure such as the Intel NetStructure
Switched Platform. Resource management and database information can be synchronized between
the processor boards via 100Mbps Ethernet communications channel C (available on each ZT 5524
/ MPCBL5524 Faceplate at J11. For more information, see
The ZT 5524 / MPCBL5524 contains one CompactPCI segment and associated control logic. The
optional ZT 4901 Bridge Mezzanine board contains a second segment and its associated control
logic.
PCI-to-PCI (P2P) bridges provide the interface to the two CompactPCI bus segments. The
CompactPCI Interface Controller (CIC) on the host processor board controls these bridges as
directed via several configurable registers. The CIC isolates the bus segments controlled by each
processor board from the other processor board. Arbitration of the CompactPCI buses is provided
by additional logic on the host processor board.
When a fault is detected, the configuration of the appropriate register determines whether it reports
a Minor, Major, or Critical fault. The register can be configured to indicate a failure due to any of
the following events:
•
•
•
•
®
Appendix B, “System
Support for independent primary and secondary PCI clocks
64-bit PCI operation
33 MHz or 66 MHz PCI bus operation
Master Reset (MRST) from the BMC power monitor and self-reset
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Appendix E, “Intelligent Platform Management Interface (IPMI)”
Registers,”for specific information.
Appendix E, “Data Sheet
®
for information on ZT 5524 / MPCBL5524
ZT 5085 12U Redundant Host Packet
Figure 1 on page
Reference”. See
13).
for more
Introduction
17