MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 79

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B.1.10
B.1.11
B.2
Intel NetStructure
Table 43. HCDATA Bit Description
Table 44. INT Bit Descriptions
HCDATA - Host Control Function Data (E7h)
I/O Address
Reset
Default Value
Size
Attribute
INT- Interrupt Status and Mask Register (E8h)
I/O Address
Reset
Default Value
Size
Attribute
Host Control Function Registers
For added register security, an index and data register pair is used to access the Host Control
Function (HCF) Registers. Each of these registers is addressed by the value in the HCINDEX
Register at I/O Address E6h. Data access is provided via the HCDATA Register.
Bit
7:6
Bit
7:0
5
4
3
2
1
0
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Reserved.
ENUM Interrupt Mask. If this bit is set, an external interrupt will not be issued
when a device on the backplane asserts ENUM.
ENUM Interrupt Flag. If this bit is set, an interrupt has been issued because of
ENUM being asserted by a device on the backplane. Clear at the source device.
CICBS Interrupt Mask. If set, an interrupt will not be issued because of a change
in the CICBS register (HCINDEX 03h).
CICBS Flag. If set, a change in the CICBS register has occurred. If the Interrupt
Mask is cleared, an interrupt will be asserted. Write 1 to this bit to clear.
CICAS Interrupt Mask. If set, an interrupt will not be issued because of a change
in the CICAS register (HCINDEX 01h).
CICAS Flag. If set, a change in the CICAS register has occurred. If the Interrupt
Mask is cleared, an interrupt will be asserted. Write 1 to this bit to clear.
This register provides access to the Host Control Function Registers. The particular register accessed
is determined by the offset value in the HCINDEX register.
E7h
PCIRST
NA
8 bits
R/W
E8h
PCIRST
04h
8 bits
RO, R/W
Description
Description
System Registers
Access
R/W1C
R/W1C
None
R/W
R/W
R/W
RO
Default
XX
1
0
1
0
1
0
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