MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 47

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Watchdog Timer
6.1
Intel NetStructure
Figure 7. Watchdog Timer Architecture
This chapter explains the operation of the ZT 5524 / MPCBL5524 Watchdog Timer. It provides an
overview of watchdog operation and features, as well as sample code to help you learn how the
Watchdog Timer works with applications.
Overview
The primary function of the Watchdog Timer is to monitor ZT 5524 / MPCBL5524 operation and
take corrective action if the system fails to function as programmed. The major features of the
watchdog timer are:
The ZT 5524 / MPCBL5524’s custom watchdog timer circuit is implemented in a programmable
logic device. The watchdog timer contains a Control and Status register (referred to in this
document as the Watchdog register, Port 79h. See
Watchdog register description).
The register allows the BIOS or user application to determine the source of a particular reset
(watchdog time-out, power-up, power out-of-range/low voltage, etc.). When the watchdog times
out, it drives an NMI and RST. Watchdog NMI and RST can be independently disabled through the
Watchdog register.
Eight timeout intervals are selectable from the Watchdog register, ranging from a minimum
timeout period of 250 ms to a maximum timeout period of 256 seconds. The watchdog is strobed
by reading the Watchdog register. This resets the timer. If the timer is not reset within the timeout
interval, the watchdog timer drives an NMI followed by RST 250 ms later. The NMI gives the
application 250 ms to perform essential tasks before the hardware is reset.
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Two-stage operation
Enabled and disabled through software control
Armed and strobed through software control
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Address/Data
Slow Clock
Port 79h
Control
and Status
Register
Appendix B, “System Registers”
Watchdog Circuit
Counter
Watchdog Timer
for the
Reset
NMI
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