MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 49

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.4.1.2
6.4.1.3
6.4.2
Intel NetStructure
Setting the Terminal Count
The terminal count determines how long the watchdog waits for a strobe before resetting the
hardware. C code for setting the terminal count might look like the following:
#define WD_CSR_IO_ADDRESS
#define WD_T_COUNT_MASK
#define WD_500MS_T_COUNT
#define WD_1S_T_COUNT
#define WD_250MS_T_COUNT
.
void SetTerminalCount(void){
Unsigned char WdValue;
WdValue = inb(WD_CSR_IO_ADDRESS);
WdValue &= ~ WD_T_COUNT_MASK;
WdValue |= WD_500MS_T_COUNT;
outb(WD_CSR_IO_ADDRESS,WdValue);
}
Strobing the Watchdog
Once the watchdog is enabled, it must be strobed within the terminal count period to avoid
resetting the system hardware. C code to strobe the watchdog might look like the following:
void StrobeWatchdog(void){
inb(WD_CSR_IO_ADDRESS);
}
Watchdog NMI
When enabled, an NMI precedes a watchdog reset by 250 ms. The NMI generation feature gives
the application 250 ms to perform essential tasks before the hardware is reset. Before using
watchdog NMI, ensure the following:
•
•
•
®
The code for performing the essential tasks is included in an interrupt service routine (ISR)
The ISR is chained to the existing NMI ISR
The watchdog NMI is enabled
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
0x79
0x07
0x01
0x00
0x00
// Holds watchdog register values.
//
// Get the current contents of the watchdog
// register.
// Mask out the terminal count bits.
// Set the desired terminal count.
// Furnish the watchdog register with the new
// IO address of the watchdog
// Bit mask for terminal count bits.
// Terminal count values . . . .
//
//
// A single read is all it takes.
// count value.
Watchdog Timer
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