ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 9

• Manufacturer Part Number: ADF4002BCPZ
• Description: IC PLL FREQUENCY SYNTH 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF), Phase Detectorr

Specifications of ADF4002BCPZ

• Design Resources: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4002 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 18 shows the full truth table. Figure 14 shows the
MUXOUT section in block diagram form.
ANALOG LOCK DETECT
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays set at high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle. For PFD frequencies greater than 10 MHz,
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 14. MUXOUT Circuit
MUX
CONTROL
DGND
DV
DD
MUXOUT
Rev. A | Page 9 of 20
analog lock detect is more accurate because of the smaller pulse
widths.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output is high with narrow,
low going pulses.
INPUT SHIFT REGISTER
The ADF4002 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 13-bit N counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram (see Figure 2). Table 6
provides the truth table for these bits. Figure 15 shows a
summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
C2
0
0
1
1
Control Bits
C1
0
1
0
1
Data Latch
R Counter
N Counter
Function Latch
Initialization Latch
ADF4002