ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 2

• Manufacturer Part Number: ADF4002BCPZ
• Description: IC PLL FREQUENCY SYNTH 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF), Phase Detectorr

Specifications of ADF4002BCPZ

• Design Resources: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4002
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
REVISION HISTORY
4/07—Rev. 0 to Rev. A
Changes to Features List .................................................................. 1
Changes to Table 1............................................................................ 3
Deleted Figure ................................................................................... 7
Changes to Figure 16...................................................................... 11
4/06—Revision 0: Initial Version
Timing Characteristics ................................................................ 4
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Reference Input Section............................................................... 8
RF Input Stage............................................................................... 8
N Counter...................................................................................... 8
R Counter ...................................................................................... 8
Phase Frequency Detector (PFD) and Charge Pump.............. 8
Rev. A | Page 2 of 20
Latch Maps and Descriptions ....................................................... 10
Applications..................................................................................... 17
Outline Dimensions ....................................................................... 19
MUXOUT and Lock Detect.........................................................9
Input Shift Register .......................................................................9
Latch Summary........................................................................... 10
Reference Counter Latch Map.................................................. 11
N Counter Latch Map................................................................ 12
Function Latch Map................................................................... 13
Initialization Latch Map ............................................................ 14
Function Latch............................................................................ 15
Initialization Latch ..................................................................... 16
Very Low Jitter Encode Clock for High Speed Converters... 17
PFD............................................................................................... 17
Interfacing ................................................................................... 17
PCB Design Guidelines for Chip Scale Package .................... 18
Ordering Guide .......................................................................... 19