ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 6

• Manufacturer Part Number: ADF4002BCPZ
• Description: IC PLL FREQUENCY SYNTH 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF), Phase Detectorr

Specifications of ADF4002BCPZ

• Design Resources: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4002
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
Figure 3. TSSOP Pin Configuration (Top View)
CPGND
AGND
RF
RF
REF
AV
R
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
SET
IN
IN
CP
DD
SET
P
IN
B
A
IN
IN
DD
DD
IN
B
A
1
2
3
4
5
6
7
8
(Not to Scale)
ADF4002
TOP VIEW
PIN 1
INDICATOR
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
where R
Charge Pump Output. When enabled, this provides ±I
external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the RF input.
Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 11.
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to the AV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can
be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches; the latch is selected using the control bits.
Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
Charge Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
16
15
14
13
12
10
11
9
I
DV
V
MUXOUT
LE
DATA
CLK
CE
DGND
CP
P
DD
SET
MAX
= 5.1 kΩ and I
=
25.5
R
SET
CP MAX
Rev. A | Page 6 of 20
= 5 mA.
SET
pin is 0.66 V. The relationship between I
DD
DD
CP
must be the same value as AV
Figure 4. LFCSP Pin Configuration (Top View)
pin. AV
to the external loop filter that, in turn, drives the
CPGND 1
AGND 2
AGND 3
RF
RF
IN
IN
B
A
4
5
DD
must be the same value as DV
(Not to Scale)
ADF4002
DD
TOP VIEW
PIN 1
INDICATOR
/2 and a dc equivalent input
DD
. In systems where V
CP
and R
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
DD
SET
.
is
DD
is 3 V, it can
DD
.