ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 4

IC PLL FREQUENCY SYNTH 20-LFCSP

ADF4002BCPZ

Manufacturer Part Number
ADF4002BCPZ
Description
IC PLL FREQUENCY SYNTH 20-LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF), Phase Detectorr
Datasheet

Specifications of ADF4002BCPZ

Design Resources
Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
400MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
400MHz
Pll Type
Frequency Synthesis
Frequency
400MHz
Supply Current
5mA
Supply Voltage Range
2.7V To 3.3V
Digital Ic Case Style
LFCSP
No. Of Pins
20
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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ADF4002
TIMING CHARACTERISTICS
AV
unless otherwise noted.
Table 2.
Parameter
t
t
t
t
t
t
1
2
Timing Diagram
1
2
3
4
5
6
Guaranteed by design, but not production tested.
Operating temperature range (B version) is −40°C to +85°C.
DD
= DV
DD
= 3 V ± 10%, AV
1
DATA
CLK
LE
LE
DD
≤ V
DB23 (MSB)
Limit (B Version)
10
10
25
25
10
20
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
t
1
DB22
2
t
2
Figure 2. Timing Diagram
Rev. A | Page 4 of 20
DB2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t
3
t
DB1 (CONTROL
4
BIT C2)
Test Conditions/Comments
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
(CONTROL BIT C1)
t
5
DB0 (LSB)
t
6
A
= T
MAX
to T
MIN
,

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