ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet

IC PLL FREQUENCY SYNTH 20-LFCSP

ADF4002BCPZ

Manufacturer Part Number
ADF4002BCPZ
Description
IC PLL FREQUENCY SYNTH 20-LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF), Phase Detectorr
Datasheet

Specifications of ADF4002BCPZ

Design Resources
Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
400MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
400MHz
Pll Type
Frequency Synthesis
Frequency
400MHz
Supply Current
5mA
Supply Voltage Range
2.7V To 3.3V
Digital Ic Case Style
LFCSP
No. Of Pins
20
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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FEATURES
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
tuning voltage in 3 V systems
REF
RF
RF
DATA
CLK
IN
IN
LE
IN
A
B
24-BIT INPUT
REGISTER
SD
OUT
AV
CE
DD
P
22
) allows extended
AGND DGND
DV
DD
R COUNTER
R COUNTER
N COUNTER
N COUNTER
FUNCTION
LATCH
LATCH
LATCH
14-BIT
13-BIT
FUNCTIONAL BLOCK DIAGRAM
14
Phase Detector/Frequency Synthesizer
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the part can be used as a standalone PFD and charge pump.
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
V
P
SD
CPGND
AV
OUT
DD
CPI3 CPI2 CPI1
©2006–2007 Analog Devices, Inc. All rights reserved.
SETTING 1
CURRENT
M3 M2 M1
MUX
REFERENCE
CHARGE
PUMP
ADF4002
CPI6 CPI5 CPI4
HIGH Z
SETTING 2
CURRENT
R
SET
ADF4002
www.analog.com
CP
MUXOUT

Related parts for ADF4002BCPZ

ADF4002BCPZ Summary of contents

Page 1

FEATURES 400 MHz bandwidth 2 3.3 V power supply Separate charge pump supply (V ) allows extended P tuning voltage systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and ...

Page 2

ADF4002 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin ...

Page 3

SPECIFICATIONS ± 10%, AV ≤ V ≤ 5.5 V, AGND = DGND = CPGND = unless otherwise noted. A MAX MIN ...

Page 4

ADF4002 TIMING CHARACTERISTICS ± 10%, AV ≤ V ≤ 5.5 V, AGND = DGND = CPGND = unless otherwise noted. Table 2. Parameter Limit (B Version) ...

Page 5

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND Digital I/O Voltage to GND Analog I/O Voltage ...

Page 6

ADF4002 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS R 1 PIN SET INDICATOR CPGND MUXOUT 3 14 ADF4002 AGND TOP VIEW DATA (Not to Scale) IN CLK RF ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS 0 –5 –10 –15 –20 +25°C +85°C –25 –30 –40°C –35 –40 0 100 200 300 FREQUENCY (MHz) Figure 5. RF Input Sensitivity 0 –5 –40°C +25°C –10 +85°C –15 –20 – ...

Page 8

ADF4002 THEORY OF OPERATION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. ...

Page 9

MUXOUT AND LOCK DETECT The output multiplexer on the ADF4002 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 18 shows the ...

Page 10

ADF4002 LATCH MAPS AND DESCRIPTIONS LATCH SUMMARY ANTI- TEST BACKLASH RESERVED MODE BITS WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 LDP T2 T1 ABP2 RESERVED DB23 DB22 DB21 DB20 ...

Page 11

REFERENCE COUNTER LATCH MAP TEST BACKLASH RESERVED MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 LDP T2 T1 ABP2 DON’T CARE ABP2 TEST ...

Page 12

ADF4002 N COUNTER LATCH MAP RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 B13 B12 B11 B10 X = DON’T CARE N13 N12 N11 ...

Page 13

FUNCTION LATCH MAP CURRENT CURRENT RESERVED SETTING SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 14

ADF4002 INITIALIZATION LATCH MAP CURRENT CURRENT RESERVED SETTING SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 15

FUNCTION LATCH With C2, C1 set the on-chip function latch is programmed. Figure 18 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When this bit is ...

Page 16

ADF4002 Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. See Figure 18 for the truth table. PD Polarity This bit sets ...

Page 17

APPLICATIONS VERY LOW JITTER ENCODE CLOCK FOR HIGH SPEED CONVERTERS Figure 20 shows the ADF4002 with a VCXO to provide the encode clock for a high speed analog-to-digital converter (ADC). The converter used in this application is an AD9215-80, a ...

Page 18

ADF4002 ADuC812 Interface Figure 22 shows the interface between the ADF4002 and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI ...

Page 19

... ADF4002BRUZ −40°C to +85°C 1 ADF4002BRUZ-RL −40°C to +85°C 1 ADF4002BRUZ-RL7 −40°C to +85°C 1 ADF4002BCPZ −40°C to +85°C 1 ADF4002BCPZ-RL −40°C to +85°C 1 ADF4002BCPZ-RL7 −40°C to +85°C EVAL-ADF4002EBZ1 1 1 EVAL-ADF411XEBZ1 RoHS Compliant Part. 5.10 5.00 4. 4.50 6.40 4.40 BSC 4 ...

Page 20

ADF4002 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06052-0-4/07(A) Rev Page ...

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