ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 16

• Manufacturer Part Number: ADF4002BCPZ
• Description: IC PLL FREQUENCY SYNTH 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF), Phase Detectorr

Specifications of ADF4002BCPZ

• Design Resources: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4002
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. See Figure 18 for the truth table.
PD Polarity
This bit sets the phase detector polarity bit (see Figure 18).
CP Three-State
This bit controls the CP output pin. Setting the bit high puts the
CP output into three-state. With the bit set low, the CP output
is enabled.
INITIALIZATION LATCH
The initialization latch is programmed when C2, C1 = 1, 1. This
is essentially the same as the function latch (programmed when
C2, C1 = 1, 0).
However, when the initialization latch is programmed there is
an additional internal reset pulse applied to the R and N
counters. This pulse ensures that the N counter is at load point
when the N counter data is latched and the device begins
counting in close phase alignment.
If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; and PD2 bit is low), the internal
pulse also triggers this power-down. The prescaler reference
and the oscillator input buffer are unaffected by the internal
reset pulse, thereby maintaining close phase alignment when
counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is reactivated. However, successive AB
counter loads after this do not trigger the internal reset pulse.
Device Programming After Initial Power-Up
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
1.
2.
3.
4.
5.
Apply V
Program the initialization latch (11 in two LSBs of input
word). Make sure that the F1 bit is programmed to 0.
Conduct a function latch load (10 in two LSBs of the
control word). Make sure that the F1 bit is programmed to 0.
Perform an R load (00 in two LSBs).
Perform an N load (01 in two LSBs).
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When the initialization latch is loaded, the following occurs:
•
•
•
CE Pin Method
1.
2.
3.
4.
5.
6.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled, as
long as it has been programmed at least once after V
initially applied.
Counter Reset Method
1.
2.
3.
4.
5.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.
The function latch contents are loaded.
An internal pulse resets the R, N, and timeout counters to
load state conditions and three-states the charge pump.
Note that the prescaler band gap reference and the oscilla-
tor input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.
Latching the first N counter data after the initialization
word activates the same internal reset pulse. Successive N
loads do not trigger the internal reset pulse unless there is
another initialization.
Apply V
Bring CE low to put the device into power-down. This is an
asynchronous power-down because it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the N counter latch (01).
Bring CE high to take the device out of power-down. The
R and N counters resume counting in close alignment.
Note that after CE goes high, a duration of 1 μs can be
required for the prescaler band gap voltage and oscillator
input buffer bias to reach steady state.
Apply V
Do a function latch load (10 in two LSBs). As part of this
step, load 1 to the F1 bit. This enables the counter reset.
Perform an R counter load (00 in two LSBs).
Perform an N counter load (01 in two LSBs).
Do a function latch load (10 in two LSBs). As part of this
step, load 0 to the F1 bit. This disables the counter reset.
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