ADF4002BCPZ Analog Devices Inc, ADF4002BCPZ Datasheet - Page 14

• Manufacturer Part Number: ADF4002BCPZ
• Description: IC PLL FREQUENCY SYNTH 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF), Phase Detectorr

Specifications of ADF4002BCPZ

• Design Resources: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4002EBZ1 - BOARD EVAL FOR ADF4002
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4002
INITIALIZATION LATCH MAP
DB23
RESERVED
X
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
DB22
X
CE PIN
0
1
1
1
DB21
PD2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
CPI6
CPI6
CPI3
0
0
0
0
1
1
1
1
CURRENT
SETTING
PD2
X
X
0
1
CPI5
2
CPI5
CPI2
0
0
1
1
0
0
1
1
CPI4
PD1
X
0
1
1
CPI3
CURRENT
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SETTING
CP14
CPI1
0
1
0
1
0
1
0
1
CPI2
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
1
CPI1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1.088
2.176
3.264
4.352
5.440
6.528
7.616
8.704
3kΩ
TC4
TIMER COUNTER
TC3
Figure 19. Initialization Latch Map
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CONTROL
I
CP
5.1kΩ
0.625
1.250
1.875
2.500
3.125
3.750
4.375
5.000
(mA)
TC2
Rev. A | Page 14 of 20
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TC1
0.294
0.588
0.882
1.176
1.470
1.764
2.058
2.352
11kΩ
F5
F4
0
1
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
DB9
SEE PAGE 16
F4
F5
X
0
1
F3
0
1
DB8
F3
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
DB7
F2
0
1
F2
M3
0
0
0
0
1
1
1
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
DB6
M3
CONTROL
MUXOUT
DB5
M2
M2
0
0
1
1
0
1
1
0
DB4
M1
DB3
PD1
M1
0
1
0
1
0
1
0
1
F1
0
1
DB2
F1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
COUNTER
OPERATION
NORMAL
R COUNTER AND
N COUNTER
HELD IN RESET
DD
C2 (1) C1 (1)
DB1
CONTROL
BITS
DB0