ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 3

• Manufacturer Part Number: ICS9LPRS525AGILF
• Description: IC CK505 VREG/RES 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS9LPRS525AGILF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1932

Pin Description (continued)
IDT
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
ICS9LPRS525
PC MAIN CLOCK
TM
PC MAIN CLOCK
SRCC3_LRS/CR#_D
VDDSRCIO
SRCT4_LRS
SRCC4_LRS
CPU_STOP#/SRCC5_LRS
PCI_STOP#/SRCT5_LRS
VDDSRC
SRCC6_LRS
SRCT6_LRS
GNDSRC
SRCC7_LRS/CR#_E
SRCT7_LRS/CR#_F
VDDSRCIO
CPUC2_ITP_LRS/SRCC8_LRS
CPUT2_ITP_LRS/SRCT8_LRS
NC
VDDCPUIO
CPUC1_F_LRS
CPUT1_F_LRS
GNDCPU
CPUC0_LRS
CPUT0_LRS
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
PIN NAME
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
N/A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair
0 = CRD# controls SRC1 pair (default),
1= CRD# controls SRC4 pair
Power supply for SRC outputs. 1.05V to 3.3V.
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
Stops all CPUCLK, except those set to be free running clocks /
Complement clock of low power differential SRC pair with 33 ohm integrated Rs.
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair
with integrated 33 ohm Rs.
Supply for SRC PLL, 3.3V nominal
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
Ground pin for the SRC outputs
Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default
is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock
Request Pin, the SR
Power supply for SRC outputs. 1.05V to 3.3V.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
Power supply for CPU outputs, 1.05V to 3.3V.
Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.
True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.
Ground pin for the CPU outputs
Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.
True clock of low power differential CPU clock pair with integrated 33 ohm Rs.
Supply for CPU PLL, 3.3V nominal
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Byte 5, bit 0
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
3
DESCRIPTION
1484C—04/20/10