ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 6

• Manufacturer Part Number: ICS9LPRS525AGILF
• Description: IC CK505 VREG/RES 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS9LPRS525AGILF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1932

IDT
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2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
10
meets Clock# falling. The median cross point is used to calculate the voltage
1
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
AC Electrical Characteristics - Low Power Differential Outputs
Clock Jitter Specs - Low Power Differential Outputs
Signal is required to be monotonic in this region.
Measurement taken for single ended waveform on a component test board (not in system)
Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance
input leakage current does not include inputs with pull-up or pull-down resistors
3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
Intentionally blank
Maximum VIH is not to exceed VDD
Operation under these conditions is neither implied, nor guaranteed.
Frequency Select pins which have tri-level input
PCI3/CFG0 is optional
Measurement taken from differential waveform on a component test board. (not in system)
Slew rate emastured through V_swing voltage range centered about differential zero
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
Only applies to the differential rising edge (Clock rising, Clock# falling)
Human Body Model
Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.
The max voltage including overshoot.
The min voltage including undershoot.
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising
ICS9LPRS525
PC MAIN CLOCK
TM
PC MAIN CLOCK
CPU Jitter - Cycle to Cycle
SRC Jitter - Cycle to Cycle
DOT Jitter - Cycle to Cycle
Differential Voltage Swing
Maximum Output Voltage
Minimum Output Voltage
Crossing Point Variation
Falling Edge Slew Rate
Rising Edge Slew Rate
Crossing Point Voltage
CPU[2_ITP:0] Skew
Slew Rate Variation
SRC[10:0] Skew
CPU[1:0] Skew
PARAMETER
PARAMETER
Duty Cycle
CPUSKEW10
CPUSKEW20
VXABSVAR
SRCSKEW
CPUJC2C
SRCJC2C
DOTJC2C
SYMBOL
SYMBOL
VSWING
tSLVAR
VXABS
VHIGH
VLOW
DCYC
tSLR
tFLR
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
6
CONDITIONS
CONDITIONS
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Averaging on
Averaging on
Averaging on
MIN
-300
MIN
300
300
2.5
2.5
45
MAX
1150
3000
MAX
550
140
100
150
125
250
20
55
85
4
4
1484C—04/20/10
UNITS NOTES
UNITS NOTES
V/ns
V/ns
mV
mV
mV
mV
mV
ps
ps
ps
ps
ps
ps
%
%
1, 10
1,4,5
1,4,9
2, 3
2, 3
1,7
1,8
1,6
2
2
1
1
1
1
1