ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 5

• Manufacturer Part Number: ICS9LPRS525AGILF
• Description: IC CK505 VREG/RES 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS9LPRS525AGILF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1932

IDT
1
2
3
Absolute Maximum Ratings - DC Parameters
Electrical Characteristics - Input/Supply/Common Output DC Parameters
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied, nor guaranteed.
Maximum input voltage is not to exceed VDD
Low Threshold Input- FSA,FSB = '1'
Low Threshold Input- High Voltage
ICS9LPRS525
PC MAIN CLOCK
Current sinking at V
Low Threshold Input-Low Voltage
TM
Low Threshold Input- FSC = '1'
Maximum SMBus Operating
PC MAIN CLOCK
Maximum Supply Voltage
Maximum Supply Voltage
Ambient Operating Temp
Operating Supply Current
Low-level Output Voltage
Maximum Input Voltage
Minimum Input Voltage
Input Leakage Current
Input Leakage Current
Clock/Data Rise Time
Storage Temperature
Input ESD protection
Clock/Data Fall Time
Output High Voltage
Output Low Voltage
iAMT Mode Current
Powerdown Current
Case Temperature
Input High Voltage
Input Capacitance
Input Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Frequency
Clk Stabilization
Supply Voltage
Supply Voltage
Pin Inductance
SMBus Voltage
Tdrive_CR_off
PARAMETER
PARAMETER
Tdrive_CR_on
SCLK/SDATA
SCLK/SDATA
Tdrive_CPU
Frequency
Trise_SE
Tfall_SE
Voltage
Voltage
OLSMB
= 0.4 V
VDDxxx_IO
VDDxxx_IO
SYMBOL
V
V
ESD prot
SYMBOL
V
V
Tambient
VDDxxx
V
VDDxxx
V
I
T
I
IH_FS_FSAB
T
IH_FS_TEST
I
DDiAMT3.3
I
IH_FS_FSC
IL_CFGMID
I
DDiAMTIO
I
T
V
F
I
IL_CFGLO
DDOP3.3
V
V
V
DDPD3.3
DRCROFF
V
IL_CFGHI
I
DDOPIO
DDPDIO
T
V
DRCRON
T
T
PULLUP
C
T
T
C
V
INRES
DRSRC
SMBUS
V
Ts
Tc
V
OLSMB
L
C
IL_FS
OHSE
OLSE
STAB
IHSE
I
FALL
RISE
ILSE
F
RI2C
FI2C
OUT
IH
INX
IL
IN
pin
DD
IN
i
Fall/rise time of all 3.3V control inputs from 20-80%
From VDD Power-Up or de-assertion of PD to 1st
Inputs with pull up or pull down resistors
Low-Voltage Differential I/O Supply
Full Active, C
Low-Voltage Differential I/O Supply
Full Active, C
Single-ended outputs, I
Single-ended outputs, I
Output stop after CR deasserted
Power down mode, 3.3V Rail
Output run after CR asserted
Power down mode, IO Rail
PCI_STOP# de-assertion
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
Single-ended 3.3V inputs
Single-ended 3.3V inputs
CPU output enable after
Output pin capacitance
V
V
Human Body Model
M1 mode, 3.3V Rail
(Min VIH + 0.15) to
(Max VIL - 0.15) to
IN
IN
M1 Mode, IO Rail
(Min VIH + 0.15)
(Max VIL - 0.15)
Supply Voltage
CONDITIONS
Supply Voltage
CONDITIONS
SMB Data Pin
= V
= V
X1 & X2 pins
3.3V Inputs
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
Any Input
@ I
DD
L
L
DD ,
DD ,
clock
= Full load; Idd 3.3V
= Full load; IDD IO
= 3.3 V
-
PULLUP
-
5
V
V
IN
IN
= GND
= GND
OH
OL
= -1mA
= 1 mA
GND - 0.5
V
V
V
2000
0.9975
MIN
3.135
SS
SS
SS
-65
MIN
-200
0.7
0.7
2.4
1.3
1.5
2.4
2.7
-5
0
2
2
4
- 0.3
- 0.3
- 0.3
VDD + 0.3
V
VDD+0.3
VDD+0.3
MAX
DD
150
115
3.465
3.465
4.6
3.8
4.6
MAX
1000
0.35
200
115
400
300
100
0.8
1.5
0.9
0.1
1.8
0.4
5.5
0.4
70
55
36
10
15
10
10
10
+ 0.3
2
5
5
7
5
6
6
0
UNITS Notes
UNITS Notes
°
°
MHz
V
V
V
V
V
kHz
mA
mA
mA
mA
mA
mA
C
C
ms
mA
uA
uA
nH
°C
pF
pF
pF
ns
us
ns
ns
ns
ns
ns
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
4,5,7
4,7
4,7
4,7
6,7
9, 10
9, 10
9, 10
7
7
10
10
10
3
3
8
8
2
1
1
1484C—04/20/10