ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 15

• Manufacturer Part Number: ICS9LPRS525AGILF
• Description: IC CK505 VREG/RES 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS9LPRS525AGILF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1932

IDT
Byte 4 Output Enable and Spread Spectrum Disable Register
Byte 5 Clock Request Enable/Configuration Register
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Byte 7 Vendor ID/ Revision ID
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ICS9LPRS525
PC MAIN CLOCK
TM
PC MAIN CLOCK
Pin
Pin
Pin
Pin
SSCD_STP_CRTL
SRC0/DOT96_OE
SRC_STP_CRTL
SATA/SRC2_OE
PLL1_SSC_ON
PLL3_SSC_ON
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
CR#_A_SEL
CR#_B_SEL
CR#_C_SEL
CR#_D_SEL
CR#_A_EN
CR#_B_EN
CR#_C_EN
CR#_D_EN
CR#_E_EN
CR#_F_EN
SRC3_OE
SRC1_OE
CPU1_OE
CPU0_OE
Reserved
Reserved
Reserved
Reserved
(SRC1)
Name
Name
Name
Name
If set, SRCs (except SRC1) stop with PCI_STOP#
PCI0_OE must be = 1 for this bit to take effect
If set, SSCD (SRC1) stops with PCI_STOP#
Sets CR#_A to control either SRC0 or SRC2
Enable PLL1's spread modulation
Enable PLL3's spread modulation
Enable CR#_E (clk req) -> SRC6
Enable CR#_F (clk req) -> SRC8
Output enable for SRC0/DOT96
Sets CR#_B -> SRC1 or SRC4
Sets CR#_C -> SRC0 or SRC2
Sets CR#_D -> SRC1 or SRC4
Output enable for SATA/SRC2
Enable CR#_A (clk req),
Output enable for SRC3
Output enable for SRC1
Output enable for CPU1
Output enable for CPU0
Enable CR#_B (clk req)
Enable CR#_C (clk req)
Enable CR#_D (clk req)
ICS is 0001, binary
Description
Description
Description
Description
Revision ID
Vendor ID
Reserved
Reserved
Reserved
Reserved
15
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
Spread Disabled
Spread Disabled
CR#_A -> SRC0
CR#_B -> SRC1
CR#_C -> SRC0
CR#_D -> SRC1
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Disable CR#_A
Disable CR#_B
Disable CR#_C
Disable CR#_D
Disable CR#_E
Disable CR#_F
Free Running
Free Running
0
0
0
0
-
-
-
-
Vendor specific
CR#_A -> SRC2
CR#_B -> SRC4
CR#_C -> SRC2
CR#_D -> SRC4
Spread Enabled
Spread Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Enable CR#_A
Enable CR#_B
Enable CR#_C
Enable CR#_D
Enable CR#_E
Enable CR#_F
PCI_STOP#
PCI_STOP#
Stops with
Stops with
assertion
assertion
1
1
1
1
-
-
-
-
1484C—04/20/10
Default
Default
Default
Default
X
X
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1